Glossary


A

address

(1) A number used by system software to identify a data storage location.

(2) In networking, a unique code that identifies a node to the network.

ASIC

Application-specific integrated circuit.

ATA

Advanced Technology Attachment. See also SATA.


B

bank

A bank can be:
(1) Interleaving within a single device on a DDR1 SDRAM.

(2) A pair of adjacent DIMMs.
See interleaving.

BGA

Ball grid array.

boot

The process of reading initial software into the computer.

bus

A set of conductors that connect various functional units within a computer.


C

cache

A smaller, faster accessible set of memory used to speed up operations of CPUs, storage, and networking components. Typically found within the component it serves.

CDE

Common Desktop Environment.

CD-ROM

Compact disc read-only memory. A CD-ROM drive reads data recorded on the CD-ROM optical disc.

CD-RW

Rewritable compact disc.

CODEC

(1) Coder/decoder. A CODEC uses analog-to-digital conversion and digital-to-analog conversion in the same chip.

(2) Compression/decompression. An algorithm or computer program for reducing byte consumption in large files and programs.


D

DDC2

Display data channel version 2. DDC2 is the I2C interface used to communicate with the monitor. This interface is the same for both the HD15 and DVI-I connectors.

DDR-1 SDRAM

Double data rate synchronous dynamic random access memory.

default

A preset value that is assumed to be correct unless changed by the user.

DIMM

Dual inline memory module. A printed circuit card that contains dynamic random access memory chips. See Registered DIMM.

DMA

Direct memory access. The transfer of data directly into memory without supervision of the processor. The data is passed on the bus directly between the memory and another device.

DRAM

Dynamic random-access memory. A read/write dynamic memory in which the data can be read or written in approximately the same amount of time for any memory location.

drive rails

Mounting hardware used to secure hard drives and other peripherals inside the workstation.

D-TLB

Data translation look-aside buffer.

DVD-dual

Optical drive that can read and write DVDs and CDs.

DVD-ROM

Digital versatile disc read-only memory.


E

ECC

Error checking and correction. The detection and correction of all single-bit errors, plus the detection of double-bit and some multiple-bit errors.

ECP

Extended capabilities port.

EEPROM

Electrically erasable programmable read only memory.

EMI

Electromagnetic interference. An electrical characteristic that directly or indirectly contributes to a degradation in performance of an electronic system.

EPIC-7

Texas Instruments Inc. 0.13 micron chip fabrication process.

ESD

Electrostatic discharge.

Ethernet

A type of network hardware that provides communication between systems connected directly together by transceiver taps, transceiver cables, and various cable types such as coaxial, twisted-pair, and fiber-optic.


F

flash PROM

Flash programmable read-only memory.

FPU

Floating-point unit. A device (board or integrated circuit) that performs floating-point calculations.


G

Gbit

(Gb) Gigabit. 1024 megabits. Commonly used term in Ethernet: Gigabit Ethernet.

Gbyte

(GB) Gigabyte. A gigabyte is 1024 megabytes. Usually refers to data transfer speeds or the capacity of a storage device.

GHz

Gigahertz. One billion cycles per second.

GUI

Graphical user interface.


I

I2C

Inter-integrated circuit. A chip-to-chip serial bus.

IChip2

Interrupt concentrator chip.

IEEE

Institute of Electrical and Electronics Engineers, Inc. The organization establishes standards for some computers and electrical components.

IEEE 1394

A high-speed communications protocol.

I/O

Input/output.

I-TLB

Instruction translation look-aside buffer.


J

JIO

The input/output bridge chip that uses the Jbus architecture.

JBus

The system bus developed for the UltraSPARC IIIi series of processors.


K

 

Kbyte

(KB) Kilobyte. 1024 bytes of data.


L

L2 cache

Level 2 cache.

LAN

Local area network.

leaf

Any node (location in a tree structure) that is farthest from the primary node.

LED

Light-emitting diode.


M

MAC

Media access controller. See also PHY.

Mbit

(Mb) Megabit. 1,048,576 bits.

MByte

(MB) Megabyte. One million bytes.

Mbps

Megabits per second.

MCU

Memory controller unit.

MHz

Megahertz. One million cycles per second.

MII

Media independent interface.

MUX

Multiplex, multiplexer. A multiplexer merges information from multiple signals to a single channel.


N

node

An addressable point on a network.

NVRAM

Nonvolatile random access memory. Stores system variables used by the boot PROM. Contains the system host ID number and Ethernet address. NVRAM retains the data when the workstation is powered off.


O

OpenBoot PROM

OpenBoot PROM contains the PROM monitor program, a command interpreter used for booting, resetting, low-level configuration, and simple test procedures. OpenBoot software initially boots the system to a state in which the system can further load an operating system.

OpenGL

OpenGL is an application programming interface (API) for developing portable, interactive 2D and 3D graphics applications.


P

PCI

Peripheral component interconnect. A high-performance 32- or 64-bit-wide bus with multiplexed address and data lines.

PCI-Express

Peripheral Component Interconnect Express. A scalable I/O serial bus technology with greater bandwidth than PCI and PCI-X.

PCI-X

An improvement to the PCI bus.

peripheral

Removable media assembly. A device such as a smart card reader, CD-ROM drive, DVD-ROM drive, 4-mm tape drive, or a diskette drive.

PHY

Physical access layer. Part of the digital-to-analog connection between the MAC and the physical Ethernet wire.

PID

Process ID.

POR

Power-on reset.

POST

Power-on self-test. A series of tests that verify motherboard components are operating properly. Now initiated with the post command.

PROM

Programmable read-only memory. After the PROM has been programmed, it cannot be reprogrammed. See flash PROM.


R

registered DIMM

A DIMM that includes a register buffer.

RISC

Reduced instruction set computer. A computer using the RISC architecture.


S

SAS

Serial attached SCSI.

SATA

Serial ATA.

SCSI

Small computer system interface.

SDR

Single data rate.

SDRAM

Synchronous DRAM.

SEEPROM

Serial electrically erasable programmable read only memory.

SMBus

System management bus. The SMBus protocol is a subset of the I2C protocol.

smart card

A card used for user authentication or storing individual user preferences.

snoop

A search for the latest data in memory.

Southbridge

A highly integrated system I/O chip. One of three I/O subsystem bridge chips.

SPOR

System power-on reset.

SPP

Standard parallel port.

SRAM

Static random access memory.

SunVTS

A diagnostic application for testing hardware.

superscalar

A processor that can execute more than one instruction per cycle.

superuser

A privileged account with unrestricted access to all files and commands.


T

Tip connection

A connection that enables a remote shell window to be used as a terminal to display test data from a system using the terminal interface protocol (Tip).

TPE

Twisted-pair Ethernet.

TOD

Time of day. A timekeeping integrated circuit.


U

UltraDMA

Ultra direct memory access. A DMA mode within an IDE controller.

UltraSPARC IIIi

The high-performance central processing unit used in the Sun workstations. The CPU uses SPARC V9, 64-bit reduced instruction set computer (RISC) architecture.

USB

Universal Serial Bus. USB 1.1 can transfer data up to 12 Mbps. USB 2.0 can transfer data up to 480 Mbps.

UTP

Unshielded twisted-pair.


V

VCC

Voltage at the common collector (positive [+] electrical connection).