A P P E N D I X C

Functional Description

This appendix describes the inner workings of the Sun Ultra 45 or Ultra 25 workstation. Topic include:

Section C.1, Hardware Architecture

Section C.2, Motherboard

Section C.3, Serial Ports

C.1 Hardware Architecture

This section provides an overview of the Sun Ultra 45 or Ultra 25 workstation.

C.1.1 Motherboard Layout Diagram

FIGURE C-1 shows the layout of the Sun Ultra 45 motherboard, including connector and jumper locations.

Note - The Sun Ultra 25 workstation motherboard has one CPU (CPU0) and one bank of four DIMM slots. Other aspects of the Sun Ultra 25 are the same as the Sun Ultra 45 workstation.

FIGURE C-1 Sun Ultra 45 Motherboard Diagram

C.1.2 System Block Diagram

FIGURE C-2 shows the Sun Ultra 45 workstation system diagram.

FIGURE C-2 Sun Ultra 45 Workstation System Diagram

Note - The Sun Ultra 25 workstation motherboard has one CPU (CPU0) and one bank of four DIMM slots. Other aspects of the Sun Ultra 25 are the same as the Sun Ultra 45 workstation.

C.1.3 Component Overview

This section describes some primary motherboard components.

C.1.3.1 CPU

UltraSPARC IIIi 1.6-GHz CPU for the Sun Ultra 45, UltraSPARC IIIi 1.34-GHz CPU for the Sun Ultra 25.

Integrated L1 caches (data, instruction, prefetch, and write)

Integrated 1-Mbyte L2 data cache

System bus - I/O bridge, JBus frequency up to 200 MHz.

C.1.3.2 Memory Subsystem

Integrated DDR-1 SDRAM 266-MHz memory controller

Memory - up to eight DDR-1 SDRAM 266-MHz registered DIMMs, (four per CPU) for the Sun Ultra 45, up to four DDR-1 SDRAM 266-MHz registered DIMMs, (four per CPU) for the Sun Ultra 25.

16 GBytes for dual CPU, 8 GBytes of memory for single CPU

C.1.3.3 I/O Bridge Chip

Sun Microsystems I/O bridge ASIC

JBus

200-MHz bandwidth

128-bit wide MUX address and data bus

Dual PCI buses

PCI-X compliant

8 x 64-byte I/O cache each bus

Fully associative I/O memory management unit on each bus

PCI-E 2 long connector is 16 lane capable, running 8 lanes

PCI-E 1 long connector is 16 lane capable, running 8 lanes

PCI-E 0 short connector is 8 lane capable, running at 4 lanes

C.1.3.4 I/O Subsystem

UltraDMA ATA 133 controller

AC-97 compliant audio interface

USB 2.x interface

C.1.3.5 Gigabit Ethernet

10/100/1000BASE-T Ethernet LAN controller

Integrated MAC and PHY

TABLE C-1 describes the behavior of the Ethernet status LEDs.

TABLE C-1 Twisted-Pair Ethernet LED Status
LED	Status
Green - Link	When illuminated, a link exists.
Amber - Activity	When flashing, indicates transmit or receive activity.

C.2 Motherboard

This section describes more details about the motherboard and some components.

C.2.1 Motherboard Block Diagram

FIGURE C-3 shows the block diagram for the Sun Ultra 45 motherboard.

Note - The Sun Ultra 25 workstation motherboard has one CPU (CPU0) and one bank of four DIMM slots. Other aspects of the Sun Ultra 25 are the same as the Sun Ultra 45 workstation.

FIGURE C-3 Sun Ultra 45 Motherboard B lock Diagram

C.2.2 CPU Description

The UltraSPARC IIIi processor is a high-performance, highly integrated superscalar processor. It is capable of sustained execution of four instructions per cycle, even with conditional branches and cache misses. Instructions are issued in program order to multiple functional units, and executed in parallel. Instructions from two basic blocks are issued in the same group to further increase the number of instructions executed per cycle.

The UltraSPARC IIIi CPU supports full implementation of the 64-bit SPARC-V9 architecture, a 64-bit virtual address space, and a 43-bit physical address space. The core instruction set includes graphics instructions that provide the most common operations used for two-dimensional image processing, two and three-dimensional graphics, image compression algorithms, and parallel operations on pixel data with 8- and 16-bit components.

C.2.3 Memory Controller

The memory system consists of the memory control unit (MCU) in the CPU, and two physical banks (B0 and B1) of DDR-1 synchronous DRAM memory. Only registered DIMMS are supported.

Clock buffering with a PLL is provided on the DIMMs. Each physical bank consists of two 128-bit DDR-1 SDRAM DIMMs. These two DIMMs share an 8-byte data bus and an ECC data bus. Both physical banks share an address/control bus. Since each DIMM could be dual sided (upper and lower banks), there are maximum of four data loads per physical bank. The cache line is split across the two physical banks. Both banks are controlled by the memory controller.

Note - DIMMs must always be installed in pairs.

A memory controller sends requests in the pipeline, using 16 memory banks in the Sun Ultra 45 when fully loaded, and 8 memory banks in the Sun Ultra 25 when fully loaded.

FIGURE C-4 UltraSPARC IIIi Chip Architecture

C.3 Serial Ports

The Sun Ultra 45 or Ultra 25 workstation has two serial ports.

When powering off, the Sun Ultra 45 or Ultra 25 workstation sends a Break signal out the serial ports. This break could interfere with a workstation-controlled server if the server is operating through a Tip connection. Five solutions are available:

Configure for an alternate Break key sequence on the server.

Filter the Tip connection through a network terminal concentrator.

Disable the keyboard abort on the server.

Disable the Tip connection on the server.

Permanently Disable the Keyboard Abort or Configure an Alternate Break Key Sequence on the Server

C.3.1 Configuring for an Alternate Break Key Sequence on the Server

As superuser, open a terminal window and configure the alternate Break key sequence. Type:

# kbd -a alternate

To invoke a keyboard abort, type Return, ~, Ctrl-B.

Note - You must reconfigure the alternate Break key sequence after a server power cycle.

C.3.2 Filtering the Tip Connection Through a Network Terminal Concentrator

The network terminal concentrator acts as a proxy between the Sun Ultra 45 or Ultra 25 workstation and the server under Tip control. The network terminal concentrator communicates with the host Sun Ultra 45 or Ultra 25 workstation through the Telnet protocol. If the workstation sends the BREAK signal, it is ignored by the network terminal concentrator. Additionally, the concentrator does not send the BREAK signal upon powering off.

C.3.3 Disabling the Keyboard Abort on the Server

This procedure configures the server to ignore the BREAK signal.

As superuser, open a terminal window and disable the keyboard abort. Type:

# kbd -a disable

To re-enable keyboard abort, type:

# kbd -a enable

Note - You must reconfigure the keyboard abort after a server power cycle.

C.3.4 Disabling the Tip Connection on the Server

To disable the Tip connection, turn the server key switch to the lock position.

This action prevents any serial communication with the server. To re-establish serial communications, turn the key to the unlock position.

C.3.5 Permanently Disabling the Keyboard Abort or Configuring an Alternate Break Key Sequence on the Server

1. As superuser, edit the /etc/default/kbd file.

To disable the keyboard abort, uncomment this line:

#KEYBOARD_ABORT=disable

To configure the alternate BREAK key sequence, uncomment this line:

#KEYBOARD_ABORT=alternate

2. Save the file.

3. Reinitialize the kbd drivers. Type:

# kbd -i