BIOS POST Codes

A P P E N D I X B

BIOS POST Codes

This appendix describes the BIOS POST Codes. It contains the following sections:

Section B.1, Introduction to Power-On Self-Test (POST)

Section B.2, How to Load Optimal Default Settings During BIOS/POST

Section B.3, How BIOS POST Memory Testing Works

Section B.4, Redirecting Console Output

Section B.5, Changing POST Options

Section B.6, POST Codes

Section B.7, POST Code Checkpoints

B.1 Introduction to Power-On Self-Test (POST)

The system BIOS provides a rudimentary power-on self-test. The basic devices required for the server to operate are checked, memory is tested, the Marvell disk controller (X4500), or the LSI SAS1068E disk controller (X4540), and the attached disks in slot 0 and slot 1 are probed and enumerated, and the two Intel Gigabit Ethernet controllers are initialized.

The progress of the self-test is indicated by a series of POST codes. These codes are displayed at the lower-right hand corner of the system’s VGA screen (once the self-test has progressed far enough to initialize the video monitor). However, the codes are displayed as the self-test runs and scroll off the screen too quickly to be read. An alternate method of displaying the POST codes is to redirect the output of the console to a serial port (see Section B.4, Redirecting Console Output).

The message BMC Responding is displayed at the end of POST.

B.2 How to Load Optimal Default Settings During BIOS/POST

1. Press F2 to invoke Setup.

After some screen messages, the BIOS setup utility appears.

2. Press F9, or use the arrow keys to scroll to the Exit -> Load Optimal Defaults.

A dialog box asks “Load Optimal Defaults [OK].”

3. Press Enter.

The dialog box closes.

4. Press F10 or use the arrow keys to scroll to Exit -> Save Changes and Exit.

A dialog asks if you want to save your changes and exit.

5. Press Enter to save your changes and exit the BIOS utility.

B.3 How BIOS POST Memory Testing Works

The BIOS POST memory testing is performed as follows:

1. The first megabyte of DRAM is tested by the BIOS before the BIOS code is shadowed (that is, copied from ROM to DRAM) and executed.

2. Once the code is executing in DRAM, the BIOS performs a simple memory test (a write/read of every location with the pattern 55aa55aa).

Note - This memory test is performed only if Quick Boot is not enabled from the Boot Settings Configuration screen. Enabling Quick Boot causes the BIOS to skip the memory test. See Section B.5, Changing POST Options for more information.

Note - Because the Sun Fire X4500/X4540 server can contain up to 32 GB of memory, the memory test can take several minutes. You cancel POST testing by pressing any key.

3. The BIOS polls the memory controllers for both correctable and uncorrectable memory errors and logs those errors into the service processor.

B.4 Redirecting Console Output

Use these instructions to access the service processor and to redirect the console output so that the BIOS POST codes can be read.

1. Initialize the BIOS Setup utility by pressing the F2 key while the system is performing the power-on self-test (POST).

The BIOS Main Menu screen appears.

2. Select Advanced.

The Advanced Settings screen appears.

3. Select IPMI 2.0 Configuration.

The IPMI 2.0 Configuration screen is displayed.

4. Select the LAN Configuration menu item.

5. Select the IP Assignment option that you want to use (DHCP or Static).

If you choose DHCP, the server’s IP address is retrieved from your network’s DHCP server and displayed in following format:

Current IP address in BMC : xxx.xxx.xxx.xxx

If you choose Static, assign the IP address manually using these steps:

a. Type the IP address in the IP Address field.

You can also enter the subnet mask and default gateway settings in their respective fields.

b. Select Commit and press return to make the changes.

c. Select Refresh and press return to see your new settings displayed in the Current IP address in BMC field.

6. Start a web browser and type the service processor’s IP address in the browser’s URL field.

A prompt appears.

7. Type a user name and password as follows:

User name: rootPassword: changeme

The ILOM Service Processor GUI screen appears.

8. Click the Remote Control tab.

9. Click the Redirection tab.

10. Set the color depth for the redirection console to either 6 or 8 bits.

11. Click the Start Redirection button.

The javaRConsole window appears and prompts for your user name and password again.

12. Type a user name and password as follows:

User name: rootPassword: changeme

The current POST screen is displayed.

B.5 Changing POST Options

These instructions are optional, but you can use them to change the operations that the server performs during POST testing.

1. Initialize the BIOS Setup utility by pressing the F2 key while the system is performing the POST.

The BIOS Main Menu screen appears.

2. Select the Boot menu.

3. From the Boot Settings screen, select Boot Settings Configuration.

The Boot Settings Configuration screen appears.

4. Select one or more of the following options:

TABLE B-1 POST Options
Option	Description
Quick Boot	This option causes the system to boot faster by skipping certain tests, such as the extensive memory test.
System Configuration Display	This option causes the system to display the system configuration screen before booting begins.
Quiet Boot	This option causes the system to display the Sun Microsystems logo instead of POST codes.
Language	This option is reserved for future use. Do not change.
Add On ROM Display Mode	When Quiet Boot is enabled, this option controls whether output from the Option ROM is displayed: Force BIOS (default): Remove the Sun logo and display Option ROM output Keep Current: Display the Sun logo and do not display Option ROM output.
Boot Num-Lock	This option controls how the system sets the keyboard Num-Lock during boot. Turn this option On to set the Num-Lock On (default) or Off to turn the Num-Lock Off.
Wait for F1 if Error	Enabling this option causes the system to pause the POST if it encounters an error, and wait for an operator to press the F1 key before resuming. The default of Off.
Interrupt 19 Capture	This option is reserved for future use. Do not change.
Default Boot Order	The letters in the brackets represent the boot devices. To see the letters defined, position your cursor over the field and read the definition on the right side of the screen.

B.6 POST Codes

TABLE B-2 contains descriptions of each of the POST codes, listed in the same order in which they are generated. These POST codes appear as a four-digit string that is a combination of two-digit output from primary I/O port 80 and two-digit output from secondary I/O port 81. In the POST codes listed in TABLE B-2, the first two digits are from port 81 and the last two digits are from port 80.

TABLE B-2 POST Codes
Post Code	Description
00d0	Coming out of POR, PCI configuration space initialization, enabling 8111’s SMBus.
00d1	Keyboard controller BAT, waking up from PM, saving power-on CPUID in scratch CMOS.
00d2	Disable cache, full memory sizing, and verify that flat mode is enabled.
00d3	Memory detections and sizing in boot block, cache disabled, IO APIC enabled.
01d4	Test base 512 KB memory. Adjust policies and cache first 8MB.
01d5	Boot block code is copied from ROM to lower RAM. BIOS is now executing out of RAM.
01d6	Key sequence and OEM specific method is checked to determine if BIOS recovery is forced. If next code is E0, BIOS recovery is being executed. Main BIOS checksum is tested.
01d7	Restoring CPUID; moving boot block-runtime interface module to RAM; determine whether to execute serial flash.
01d8	Decompressing runtime module into RAM. Storing CPUID information in memory.
01d9	Copying main BIOS into memory.
01da	Giving control to BIOS POST.
0004	Check CMOS diagnostic byte to determine if battery power is OK and CMOS checksum is OK. If the CMOS checksum is bad, update CMOS with power-on default values.
00c2	Set up boot strap processor for POST. This includes frequency calculation, loading BSP microcode, and applying user requested value for GART Error Reporting setup question.
00c3	Errata workarounds applied to the BSP (#78 & #110).
00c5	Enumerate and set up application processors. This includes microcode loading, and workarounds for errata (#78, #110, #106, #107, #69, #63).
00c6	Reenable cache for boot strap processor, and apply workarounds in the BSP for errata #106, #107, #69, and #63 if appropriate.
00c7	HT sets link frequencies and widths to their final values.
000a	Initializing the 8042 compatible Keyboard Controller.
000c	Detecting the presence of keyboard in KBC port.
000e	Testing and initialization of input devices. Traps the INT09h vector, so that the POST INT09h handler gets control for IRQ1.
8600	Preparing CPU for booting to OS by copying all the context of the BSP to all application processors present. NOTE: APs are left in the CLI HLT state.
de00	Preparing CPU for booting to OS by copying all the context of the BSP to all application processors present. NOTE: APs are left in the CLI HLT state.
8613	Initialize PM regs and PM PCI regs at Early-POST. Initialize multi-host bridge, if system supports it. Setup ECC options before memory clearing. Enable PCI-X clock lines in the 8131.
0024	Decompress and initialize any platform specific BIOS modules.
862a	BBS ROM initialization.
002a	Generic Device Initialization Manager (DIM) - Disable all devices.
042a	ISA PnP devices - Disable all devices.
052a	PCI devices - Disable all devices.
122a	ISA devices - Static device initialization.
152a	PCI devices - Static device initialization.
252a	PCI devices - Output device initialization.
202c	Initializing devices. Detecting and initializing the video adapter installed in the system that have optional ROMs.
002e	Initializing all the output devices.
0033	Initializing the silent boot module. Set the window for displaying text information.
0037	Displaying sign-on message, CPU information, setup key message, and any OEM-specific information.
4538	PCI devices - IPL device initialization.
5538	PCI devices - General device initialization.
8600	Preparing CPU for booting to OS by copying all the context of the BSP to all application processors present. NOTE: APs are left in the CLI HLT state.

B.7 POST Code Checkpoints

The POST code checkpoints are the largest set of checkpoints during the BIOS pre-boot process. TABLE B-3 describes the checkpoints that might occur during the POST portion of the BIOS. These two-digit checkpoints are the output from primary I/O port 80.

TABLE B-3 POST Code Checkpoints
Post Code	Description
03	Disable NMI, Parity, video for EGA, and DMA controllers. At this point, POST code is still executing out of BIOS ROM.
04	Check CMOS diagnostic byte to determine if battery power is OK and CMOS checksum is OK. Verify CMOS checksum manually by reading storage area. If the CMOS checksum is bad, update CMOS with power-on default values and clear passwords. Initialize status register A. Initializes data variables that are based on CMOS setup questions. Initializes both the 8259 compatible PICs in the system.
05	Initializes the interrupt controlling hardware (generally PIC) and interrupt vector table.
06	Do R/W test to CH-2 count register. Initialize CH-0 as system timer. Install the POSTINT1Ch handler. Enable IRQ-0 in PIC for system timer interrupt. Traps INT1Ch vector to POSTINT1ChHandlerBlock.
C0	Early CPU Init Start-Disable Cache-Init Local APIC.
C1	Set up boot strap processor information.
C2	Set up boot strap processor for POST. This includes calculating the frequency, loading BSP microcode, and applying user-requested value for GART Error Reporting setup question.
C3	Errata workarounds applied to the BSP (#78 & #110).
C5	Enumerate and set up application processors. This includes microcode loading, and workarounds for errata (#78, #110, #106, #107, #69, #63).
C6	Reenable cache for boot strap processor, and apply workarounds in the BSP for errata #106, #107, #69, and #63 if appropriate. In case of mixed CPU steppings, errors are sought and logged, and an appropriate frequency for all CPUs is found and applied. NOTE: APs are left in the CLI HLT state.
C7	The HT sets link frequencies and widths to their final values. This routine gets called after CPU frequency has been calculated to prevent bad programming.
0A	Initializes the 8042 compatible keyboard controller.
0B	Detects the presence of PS/2 mouse.
0C	Detects the presence of keyboard in KBC port.
0E	Testing and initialization of input devices. Also, update the kernel variables. Traps the INT09h vector, so that the POST INT09h handler gets control for IRQ1. Decompress all available language, BIOS logo, and Silent logo modules.
13	Initialize PM regs and PM PCI regs at Early-POST. Initialize multi-host bridge, if system supports it. Set up ECC options before clearing memory. REDIRECTION causes corrected data to written to RAM immediately. CHIPKILL provides 4-bit error det/corr of x4 type memory. Enable PCI-X clock lines in the 8131.
20	Relocate all the CPUs to a unique SMBASE address. The BSP will be set to have its entry point at A000:0. If fewer than five CPU sockets are present on a board, subsequent CPUs entry points are separated by 8000h bytes. If more than four CPU sockets are present, entry points are separated by 200h bytes. CPU module is responsible for the relocation of the CPU to correct address. NOTE: APs are left in the INIT state.
24	Decompress and initialize any platform-specific BIOS modules.
30	Initialize System Management Interrupt.
2A	Initializes various devices through DIM.
2C	Initializes various devices. For all devices, assigns resources and initializes option ROM if required.
2E	Initializes all the output devices.
31	Allocate memory for ADM module and decompress it. Give control to ADM module for initialization. Initialize language and font modules for ADM. Activate ADM module.
33	Initializes the silent boot module. Set the window for displaying text information.
37	Displaying sign-on message, CPU information, setup key message, and any OEM-specific information.
38	Initializes various devices through DIM.
39	Initializes DMAC-1 and DMAC-2.
3A	Initialize RTC date/time.
3B	Test for total memory installed in the system. Also, check for DEL or ESC keys to limit memory test. Display total memory in the system.
3C	By this point, RAM read/write test and the memory controller programming are complete.
40	Detect various devices (parallel ports, serial ports, and coprocessor in CPU, etc.) successfully installed in the system and update the BDA, EBDA, etc.
50	Programming the memory hole or any kind of implementation that needs an adjustment in system RAM size if necessary.
52	Updates CMOS memory size from memory found in memory test. Allocates memory for Extended BIOS Data Area from base memory.
60	Initializes NUM-LOCK status and programs the keyboard.
75	Initialize Int-13 and prepare for IPL detection.
78	Initializes IPL devices controlled by BIOS and option ROMs.
7A	Initializes remaining option ROMs.
7C	Generate and write contents of ESCD in NVRam.
84	Log errors encountered during POST.
85	Display errors to the user and receives the user responses.
87	Execute BIOS setup if needed/requested.
8C	After all device initialization is done, programmed any user-selectable parameters relating to NB/SB, such as timing parameters, noncacheable regions and the shadow RAM cacheability, and do any other NB/SB/PCI-X/OEM-specific programming necessary during late-POST. Background scrubbing for DRAM, and L1 and L2 caches are set up based on setup questions. Get the DRAM scrub limits from each node. Workaround for erratum #101 is applied here.
8D	Build ACPI tables (if ACPI is supported).
8E	Program the peripheral parameters. Enable/Disable NMI as selected.
90	Late POST initialization of system management interrupt.
A0	Check boot password if installed.
A1	Clean-up work required before booting to OS.
A2	Takes care of runtime image preparation for various BIOS modules. Fill the free area in F000h segment with 0FFh. Initializes the Microsoft IRQ Routing Table. Prepares the runtime language module. Disables the system configuration display if required.
A4	Initialize runtime language module.
A7	Displays the system configuration screen if enabled. Initialize the CPUs before boot, which includes the programming of the MTRRs.
A8	Prepare CPU for OS boot including final MTRR values.
A9	Wait for user input at config display if required.
AA	Uninstall POST INT1Ch vector and INT09h vector. Deinitializes the ADM module.
AB	Prepare BBS for Int 19 boot.
AC	Any kind of chipset (NB/SB)-specific programming required during end-POST, just before giving control to runtime code booting to OS. Programmed the system BIOS (0F0000h shadow RAM) cacheability. Ported to handle any OEM specific programming required during end-POST. Copy OEM-specific data from POST_DSEG to RUN_CSEG.
B1	Save system context for ACPI.
00	Prepares CPU for booting to OS by copying all of the context of the BSP to all application processors present. NOTE: APs are left in the CLIHLT state.
61-70	OEM POST Error. This range is reserved for chipset vendors and system manufacturers. The error associated with this value might be different from one platform to the next.