Sun Blade X6270 M2 Server Module Service Manual

Memory Module (DIMM) Reference

When replacing or upgrading a DIMM on the Sun Blade X6270 M2 Server Module, see the following sections:

• Memory Module Installation Considerations
• DIMM and CPU Physical Layout
• DIMM Population Rules
• DIMM Rank Classification Labels
• Error Correction and Parity
• Inconsistencies Between DIMM Fault LEDs and the BIOS Mapping of Faulty DIMMs
• Locations of Faulty DIMMs Using ILOM Versus BIOS

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D.1 Memory Module Installation Considerations

The Sun Blade X6270 M2 Server Module supports a variety of DIMM configurations that can include single-rank (SR) DIMMs, dual-rank (DR) DIMMs, or quad-rank (QR) DIMMs. When replacing or adding memory modules to the Sun Blade X6270 M2 Server Module, you should consider the following:

• Physical layout of the DIMMs and CPUs

For details, see DIMM and CPU Physical Layout.

• DIMM population rules

For details, see DIMM Population Rules.

• DIMM classification labels

For details, see DIMM Rank Classification Labels.

• Error correction and parity

For details, see Error Correction and Parity

D.1.1 DIMM and CPU Physical Layout

The physical layout of the DIMMs and CPUs on a Sun Blade X6270 M2 Server Module is shown in FIGURE D-1.

FIGURE D-1 CPU and DIMM Physical Layout

D.1.2 DIMM Population Rules

The DIMM population rules for the Sun Blade X6270 M2 Server Module are as follows:

1. Do not populate any DIMM socket next to an empty CPU socket. Each processor contains a separate memory controller.

2. Each CPU can support a maximum of:

• Nine dual-rank (DR) or single-rank (SR) DIMMs; or
• Six quad-rank (QR) DIMMs with two per memory channel; or
• Three QR DIMMs with one per channel and three DR or SR DIMMs.

3. Each CPU can support single DIMMs or two DIMMs per channel.

4. Each CPU can support a single DIMM in channel 0, or one DIMM each in channels 0 and 1.

5. A server CPU will support both 1.35v and 1.5v DIMMs, but will default to the higher voltage.

6. Populate DIMMs by location according to the following rules:

• Populate the DIMM slots for each memory channel that are the farthest from the CPU first.

For example, populate D8/D5/D2 first; then D7/D4/D1 second; and finally, D6/D3/D0. See FIGURE D-1.

• Populate QR DIMMs first, followed by SR or DR DIMMs.
• Populate QR DIMMs in blue sockets (D8/D5/D2) first then white sockets (D7/D4/D1). See FIGURE D-1.

Note that QR DIMMs are supported only in white sockets if adjacent blue socket contains a QR DIMM.

7. For maximum performance, apply the following rules:

• The best performance is ensured by preserving symmetry. For example, adding three of same kind of DIMMs, one per memory channel, and ensuring that both CPUs have the same size of DIMMs populated in the same manner.
• In certain configurations, DIMMs will run slower than their individual maximum speed. See TABLE D-1 for further details.



TABLE D-1 Memory Considerations and Limitations

1	DIMMs are available in two speeds: 1066 MHz and 1333 MHz.
2	DIMM speed rules are as follows: 3x DIMM per channel = 800 MHz 2x DIMM per channel = 1333 MHz (for single-rank and dual-rank DIMMs) or = 800 MHz (for quad-rank DIMMs) 1x DIMM per channel = 1333 MHz (if using 1333 MHz DIMMs1) 1x DIMM per channel = 1066 MHz (if using 1066 MHz DIMMs)
3	The system operates all memory only as fast as the slowest DIMM configuration.
1 This DIMM configuration requires CPUs supporting 1333 MHZ.

D.1.3 DIMM Rank Classification Labels

DIMMs come in a variety of ranks: single, dual, or quad. Each DIMM is shipped with a label identifying its rank classification. TABLE D-2 identifies the corresponding rank classification label shipped with each DIMM.

D.1.4 Error Correction and Parity

The server’s processor provides parity protection on its internal cache memories and error-correcting code (ECC) protection of the data. The system can detect and log the following types of errors:

• Correctable and uncorrectable memory ECC errors
• Uncorrectable CPU internal errors

Advanced ECC corrects up to 4 bits in error on nibble boundaries, as long as they are all in the same DRAM. If a DRAM fails, the DIMM continues to function.

Refer to the Oracle Integrated Lights Out Manager (ILOM) 3.0 Documentation Collection for information on how to access the error log.

D.1.5 Inconsistencies Between DIMM Fault LEDs and the BIOS Mapping of Faulty DIMMs

When a single DIMM is marked as faulty by ILOM (for example, fault.memory.intel.dimm.training-failed is listed in the SP Event Log), BIOS might map out the entire memory channel that contains the faulty DIMM as failing, that is, up to three DIMMs. As a result, the memory available to the operating system is reduced.

However, when the Fault Remind button is pressed, only the fault LED associated with the faulty DIMM lights. The fault LEDs for the other two DIMMs in the memory channel remain off. Therefore, you can correctly identify the faulty DIMM. When the faulty DIMM is replaced and the DIMM fault is cleared using ILOM, the memory available to the operating system returns to normal. For instructions for clearing DIMM faults, see the Oracle Integrated Lights Out Manager (ILOM) 3.0 Supplement for the Sun Blade X6270 M2 Server Module (821-0501).

D.1.6 Locations of Faulty DIMMs Using ILOM Versus BIOS

ILOM and BIOS use different formats to identify the location of a faulty DIMM.

• For ILOM, the format is Px/Dx, where x is 0 or 1 for CPUs, and 0 to 8 for DIMMs.
• For BIOS, the format is CPUx/CHANNELx/DIMMx, where x is 0 or 1 for CPUs, and 0 to 2 for channels and DIMMs.

TABLE D-3 shows the mapping of faulty DIMM locations as reported by ILOM and BIOS.

Sun Blade X6270 M2 Server Module Service Manual

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