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Normal Mode page 3-1 Full Diagnostic Mode page 3-2 Tests POST Runs page 3-5 POST Error Messages page 3-8 Status Lights (LEDs) and Indicators page 3-8 After POST Ends page 3-10 -------------------------------------------------
The Power-On Self-Test (POST) diagnostics reside in the OpenBoot PROM located on the system board. There are two POST modes: Normal and Diagnostic.
Under Normal mode, when the system is turned on, control is sent to the OpenBoot PROM. Depending on the options set in the OpenBoot PROM, for example if autoboot is enabled (set to true), the operating system will load. Diagnostic testing is not run.
Diagnostic mode, which tests the major hardware system board components and the installed MBus modules, runs if one of these conditions are met:
Note - In Open Boot PROM version 2.14 or later versions, POST runs an abbreviated set of tests when the keyboard is disconnected.
The uniprocessor POST tests one MBus module. The Multiprocessor POST tests all installed MBus modules. Open Boot PROM version 2.14 or later versions contain tests for multiple MBus modules installed in the system. Versions prior to 2.14 only test MBus module 0, processor 0 (mid=8). POST detects only major failures.
To view test progress and view error messages returned by POST, connect a terminal to serial port A or use a tip connection to another workstation.
If you do not connect a terminal to serial port A or use a tip connection, the screen will be blank during the POST Diagnostic test mode. In this case, use the keyboard LEDs to display error conditions. See Section 3.6, "Status Lights (LEDs) and Indicators."
A brief Power-On Self-Test (POST) is run if you disconnect the keyboard and you set the diag-switch? NVRAM parameter to false in the OpenBoot PROM. The brief Power-On Self-Test is silent (no progressive test messages are printed out.) If an error or errors occur during the abbreviated Power-On Self- Test, all error messages are displayed on the TTY or tip window. If no errors occur, a message similar to the following is displayed on the TTY or tip window:
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CPU_#0 TI, TMSS390Z55(3.x) 1Mb External cache CPU_#1 TI, TMSS390Z55(3.x) 1Mb External cache CPU_#2 TI, TMSS390Z55(3.x) 1Mb External cache CPU_#3 TI, TMSS390Z55(3.x) 1Mb External cache <<<Power on Self Test (POST) is running . . . . <<< --------------------------------------------------------
You can use the serial port on the SPARCstation 10 to connect to another Sun` workstation (either the same type of SPARC" system or a different type of Sun workstation or server system). This connection lets you use a shell window on the Sun workstation as a terminal to the SPARCstation 10 being tested.
The tip method is recommended, because it lets you use SunOS` windowing and operating system features to help you work with the boot PROM.
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hardwire:\ :dv=/dev/ttya:br#9600:el=^C^S^Q^U^D:ie=%$:oe=^D: ---------------------------------------------------
The system will reply connected.
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hostname% tip hardwire connected ----------------------------
The shell window is now a tip window directed to the Sun Workstation serial port.
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hostname% kill -9 PID# of tip hardwire process ---------------------------------------------------
Following is a sample listing from Open Boot PROM version 2.14 or later versions of the full diagnostic mode tests completed by POST in a system with one MBus module installed.
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CPU_#0 TI, TMSS390Z55(3.x) 1Mb External cache SMCC SPARC-Station 10 Power On Self Test ver. 3.0 (7/15/93) cpu00000000 psr= 404010e6 bist-stat.sig= 00000000.3e0759de cache-ctlr= 3e0759de bist-sig= 7fffabde <<< CPU_00000000 on MBus Slot_00000000 > IS RUNNING (MID = 00000008) MMU Context Table Reg Test MMU Context Register Test MMU TLB Bit Pattern Tests MMU Flush Tests D-Cache RAM Write/Read Test D-Cache PTAG Write/Read Test D-Cache STAG Write/Read Test I-Cache RAM Write/Read Test I-Cache PTAG Write/Read Test I-Cache STAG Write/Read Test Cache Flashclear Test MXCC Register Test MXCC E-Cache Tag RAM Test MXCC E-Cache Data Ram Test (00000001 MB E$ DATA RAM, MXCC_CSR=00000000) MXCC Non-Cache Block Zero Test MXCC Non-Cache Blcok Copy Test MXCC Cacheable Block Read Test MXCC Cacheable Block Write Test EMC/SMC Control Regs Tests ECC Multiple UE Test ECC Multiple CE Test ECC Multiple CE, UE Test FPU Register File Test FPU Misaligned Reg Pair Test FPU Single-precision Tests FPU Double-precision Tests FPU SP Invalid CEXC Test FPU SP Overflow CEXC Test FPU SP Underflow CEXC Test FPU SP Divide-by-0 CEXC Test FPU SP Inexact CEXC Test -----------------------------------------------------------------------
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FPU SP Trap Priority Test FPU SP Trap Priority < Test FPU SP UE Trap Priority Test FPU DP Invalid CEXC Test FPU DP Overflow CEXC Test FPU DP Underflow CEXC Test FPU DP Divide-by-0 CEXC Test FPU DP Inexact CEXC Test FPU DP Trap Priority Test FPU DP Trap Priority < Test FPU DP UE Trap Priority Test FPU DP CE Trap Priority Test Memory Address Pattern Test System Interrupt Regs Tests PROC0 Interrupt Regs Tests Soft Interrupts OFF Test Soft Interrupts ON Test PROC0 User Timer Test PROC0 Counter/Timer Test System Counter Test MSI/MSBI Control Reg Tests IOMMU CAM NTA Pattern Test IOMMU TLB NTA Pattern Test IOMMU CAM TLB Comparator Test IOMMU TLB Flush Tests DMA2 ID Register Test DMA2 E_CSR Register Test LANCE Address Port Tests LANCE Data Port Tests DMA2 D_CSR Register Test DMA2 D_ADDR Register Test DMA2 D_BCNT Register Test DMA2 D_NADDR Register Test ESP Registers Tests DMA2 P_CSR Register Test DMA2 P_ADDR Register Test DMA2 P_BCNT Register Test PPORT Registers Tests DMA2 PPORT IO Loopback Test DMA2 PPORT XFR Loopback Test TOD Registers Test -------------------------------
The POST error messages returned to the terminal are self-explanatory. For example, if no DSIMM is installed in the system, POST will tell you that no DSIMM is installed and the slot number of the SIMM slot. Use the error messages returned by POST to troubleshoot the system.
The LED at the front of the chassis lights up when the system is operating normally. Figure 3-1 shows the location of the system LED. Chapter 4, "Troubleshooting Procedures," shows flow diagrams of actions to take when the system LED is not lit.
Figure 3-1 System LED on Front of System
This section describes the keyboard LED sequences displayed at power up when POST fails. If a failure occurs in POST, the keyboard displays a specific LED pattern. See Figure 3-2 and Table 3-1. After POST is completed and during normal system operation, the LEDs should not be interpreted as diagnostic error indicators.
Following the system initialization, the operating system boots automatically, unless the NVRAM configuration options specify not to do so.
Note - The Caps Lock key LED, located just above the left-hand Shift key, is not used as a power-on test failure indicator, but flashes on and off while POST is running.
Figure 3-2 Arrangement of the Keyboard LEDs
Table 3-1 Keyboard LED Description
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LED State Description ---------------------------------------------------------
Caps Lock flashing or lit POST is running
Num Lock on System board failed
Scroll Lock on MBus module in slot 0 failed
Compose on DSIMM in slot J0201 failed
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If the Caps Lock key fails to flash on and off after you have pressed and held the Stop (L1) -d keys when you power on the system, POST failed. MBus module 0 or a critical system board component may have failed. Also see Section 4.2.2, "System Board Test," for troubleshooting information.
Use Figure 3-3 to determine what diagnostic tests to run after the POST ends.
Figure 3-3 Tests to Run After Running POST
To run on-board diagnostics, see Chapter 2, "Troubleshooting Overview," and Appendix E, "Selected On-Board Diagnostics."
