A new tunable, kern.exec.dflThreadFpuCtrl, has been added to configure default thread behaviour on floating point exceptions. This tunable is a bit field and is the logical OR of MSR(FE0,FE1) bits and FPSCR(24-31) control bits.
The following bits may be set or cleared:
Floating-point exceptions disabled
Floating-point precise exception mode
Invalid operation exception enabled
Overflow exception enabled
Underflow exception enabled
Zero divide exception enabled
Inexact operation exception enabled
Non IEEE mode. This bit should never be set.
Round to nearest
Round toward zero
Round toward +infinity
Round toward -infinity