Support for FPU Exception Handling

A new tunable, kern.exec.dflThreadFpuCtrl, has been added to configure default thread behaviour on floating point exceptions. This tunable is a bit field and is the logical OR of MSR(FE₀,FE₁) bits and FPSCR(24-31) control bits.

The following bits may be set or cleared:

MSR(FE0,FE1)=0x00000000

Floating-point exceptions disabled

MSR(FE0,FE1)=0x00000900

Floating-point precise exception mode

FPSCR(VE)=0x00000080

Invalid operation exception enabled

FPSCR(OE)=0x00000040

Overflow exception enabled

FPSCR(UE)=0x00000020

Underflow exception enabled

FPSCR(ZE)=0x00000010

Zero divide exception enabled

FPSCR(XE)=0x00000008

Inexact operation exception enabled

FPSCR(NI)=0x00000004

Non IEEE mode. This bit should never be set.

FPSCR(RN)=0x00000000

Round to nearest

FPSCR(RN)=0x00000001

Round toward zero

FPSCR(RN)=0x00000002

Round toward +infinity

FPSCR(RN)=0x00000003

Round toward -infinity