Glossary

A

address repeater
(AR) ASIC

Used on slot 0 and slot 1 boards to implement the on-board system address bus. Connects four CPUs (or two I/O controllers) to the address controller on the expander board.

automatic system recovery (ASR)

The ability of a system to recover automatically in the event of a hardware failure. Identifies and isolates a failing hardware component, and builds a bootable system configuration without the failed hardware component.

B

board set (expander)

The combination of an expander board, a slot 0 board, and a slot 1 board.

boot bus controller (SBBC) ASIC

Used on slot 0 and slot 1 boards to provide a console-bus-slave interface to PROM bus, JTAG, and I2C devices for board initialization. When used with CPUs, provides a boot-bus path to POST code.

C

CDC

Coherency directory cache inside the system address controller (AXQ) ASIC. Caches recent memory tag states stored in the ECC bits of memory to speed up accesses to cache lines on other board sets.

concurrent service

The ability to service various parts of a machine without interfering with a running system.

Control board

Connects into one of two control slots on the Sun Fireplane interconnect. Consists of a centerplane support board, a System Control board, and a peripheral board.

CPU/Memory board

A slot 0 board that holds four CPUs, each of which controls eight DIMMs. The CPU/Memory board has an off-board bandwidth of 4.8 Gbyte/sec.

D

data arbiter (DARB) ASIC

Used on the Sun Fireplane interconnect to control the 18x18 data crossbar.

data multiplexer (DMX) ASIC

An 18x18 data crossbar that connects the system data interfaces on each expander board to the Sun Fireplane interconnect.

data path controller (SDC) ASIC

Used on the slot 0 and slot 1 boards to controls the on-board system data path. Repeats the console bus to the two on-board boot-bus controllers.

data switch (DX) ASIC

Used on the slot 0 and slot 1 boards to connect the on-board system data path to the off-board system data path.

DCDS

A dual-CPU data switch ASIC that connects two CPUs and two memory units to the data switch ASIC.

domain set

The combination of an SRD and its client domains.

domainstop

Error isolation between client domains.

dynamic reconfiguration

The process of activating or deactivating devices such as boards and power supplies in a running Solaris operating system while user applications continue.

E

expander board

A board connecting into the Sun Fireplane interconnect at the slot 0 and slot 1 sockets.

G

Gbyte/sec (Gbps)

Gigabyte per second of capacity = 230 = 1,073,741,824 bytes

H

hot-swap

An active device that can be installed and removed from a running system for dynamic reconfiguration.

hsPCI+ assembly

An assembly that holds one 33-MHz standard PCI card and three 33/66 MHz standard PCI cards. The PCI cards can be hot-swapped from the I/O slot while the system is in operation for dynamic reconfiguration.

hsPCI-X assembly

An assembly that holds one 33-MHz standard PCI card and three 33/66/90 MHz standard PCI cards. The PCI cards can be hot-swapped from the I/O slot while the system is in operation for dynamic reconfiguration.

J

JTAG

Joint Test Action Group. An IEEE standard (1149.1) for serial scanning of chip internal registers.

L

latency

The time for a single data item to be delivered from memory to a CPU.

link domains

A linked domain is when a domain is removed from an inter-domain network.

M

Mbyte

Megabyte of capacity = 220 = 1,048,576 bytes.

P

PCI controller ASIC

Used on the hsPCI-x and hsPCI+ boards and the link board to connect the system interconnect to the PCI buses.

PCI hot-swap cassette

A passive hot-swap carrier that adapts standard PCI pins to connectors.

power source

The hardware components powered by a group of power supplies.

R

recordstop

A recordstop is a nonfatal error such as correctable single-bit errors in a data path.

response multiplexer (RMX) ASIC

An 18x18 crossbar that transmits transaction responses and connects together the address controllers on each expander board.

S

scalable shared
memory (SSM)

A mode of the system interconnect that enables multiple snoopy coherence domains to be connected together.

split expander

Two system boards in a board set that are in separate domains.

Sun Fire address bus

Address bus containing a maximum snoop rate of 150 million snoops per second or a 9.6-Gbyte/sec data rate.

Sun Fireplane interconnect

The interconnect architecture used by the UltraSPARC IV Cu generation of CPUs. This architecture is the physical active-logic centerplane that implements the system address and data crossbars.

Sun Fireplane interconnect architecture

The cache-coherency protocol and set of address transactions that are used by all UltraSPARC IV Cu CPU-based systems.

Sun Fireplane interconnect data path

The point-to-point data protocol used between the DCDS and DX ASICs.

system address controller
(AXQ) ASIC

Connects the address repeaters on the slot 0 and the slot 1 boards to the Sun Fireplane interconnect address and response crossbars. Used on expander boards.

system board set

Connects into one of 18 system slots in the Sun Fireplane interconnect with the expander board. Contains slot 0 boards and slot 1 boards.

System Control board set

Connects into one of two system control slots in the Sun Fireplane interconnect with the centerplane support board. This board set contains the System Control board and a system control peripheral board ( DVD-ROM, DAT drive, hard drive).

system data interface (SDI) ASIC

Used on the expander boards to connect the data switches on the slot 0 and the slot 1 boards to the Sun Fireplane interconnect data crossbars.

U

UltraSPARC CPU

The UltraSPARC IV Cu CPU is used on the CPU/Memory board.

unlinking domains

Removing a domain from the inter-domain network.