Hardware Description

This chapter summarizes the CP2140 hardware. See Chapter 5 for a detailed functional description of the hardware.

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4.1 Physical

The CP2140 is a 6U-sized circuit card with CompactPCI connectors J1 and J2 for CompactPCI, and J3 - J5 for I/O.

• The CP2140 provides front-panel I/O through an RJ45 connector, a TTY connector, and a slot for a PMC card.
• Through the CompactPCI backplane, a transition card can be connected to provide connector access for two serial ports, two RJ45 Ethernet ports, two USB ports, one parallel port, one floppy port, PS/2 keyboard/mouse, and two SCSI ports.
• The PMC card interface accepts an IHV-supplied PMC I/O card.
• The IHV-supplied PCI Interface Module (PIM) can duplicate front-panel PMC
  I/O ports. The PIM interfaces with a transition card and enables access to I/O ports at the rear of the enclosure.

A PMC module can be installed on the CP2140. A cut-out is provided on the front-panel for the PMC card. The CP2140 front panel also provides an RJ45 Ethernet connector and a mini-DIN TTY connector. The panel includes status lamps and reset push buttons which are listed top to bottom as follows (see FIGURE 1-4):

• ABORT - push button
• RESET - push button
• ALARM/USER - red/green
• READY - green
• Blue LED for hot swap
• Front panel latch to lock and unlock the CP2140 for insertion or removal.

See for FIGURE 1-1 for the Netra CP2140 board key onboard components and FIGURE 1-4 for the front panel.

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Note - The CP2140 is shipped with the CPU, heat sink, the SMC module and the power module as integral parts of the board (see FIGURE 4-1).

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FIGURE 4-1 shows the CP2140 with the heat sink, SMC, power module, and SDRAM module.

 FIGURE 4-1 Netra CP2140 Board with Heat sink, SMC, Power Module and SDRAM Module

FIGURE 4-2 shows the solder side of the Netra CP2140 board.

 FIGURE 4-2 Solder Side of the Netra CP2140 Board

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4.2 Summary Description

A simplified CP2140 block diagram is shown in FIGURE 4-3. For detailed descriptions of on-board components, see Chapter 5.

 FIGURE 4-3 Netra CP2140 Board Functional Block Diagram

The UltraSPARC IIi processor has a 512 Kbyte 4-way set associative integrated cache.

Apart from incoming interrupts, the processor handles all I/O through its built-in 66MHz, 32-bit PCI bus interface. This interface is used to connect to an Advanced PCI Bridge (APB) that services two 33 MHz, 32-bit downstream interfaces:
PCI bus A and PCI bus B.

PCI bus A connects to a nontransparent PCI bridge (NTB) which services the principal PCI bus connection to the CompactPCI backplane through connectors J1 and J2. In a System Host role, a PCI bus arbiter provides arbitration signals for the CompactPCI backplane bus. It also supplies clocks for the CompactPCI bus. The arbiter is only active if the host board functions in a System Host role. When the board is required to function as a satellite board, the CompactPCI bus arbiter is disabled by the System Management Controller (SMC).

PCI Bus B connects the APB to each of two PCIO-2 (SouthBridge) packages: PCIO-2 A and PCIO-2 B, the Dual SCSI device and PMC slot.

PCIO-2 A provides downstream interfaces:

• Network media-independent interface (MII) A to the CompactPCI/J4 connector and to an on-board PHY package A that interfaces the front panel of RJ45
• USB A port that is routed through CompactPCI/J5 backplane connector
• The EBus is a versatile 8-bit data, 24-bit address bus similar to an ISA bus. EBus A connects to:
• NVRAM, which stores real-time clock and MAC address information
• System and user flash memory
• Main PLD, which provides EBus decodes for chip selects and CompactPCI arbiter control logic
• Super I/O PC97307 interface

PCIO-2 B provides the following interfaces:

• Network MII B to the CompactPCI/J4 connector
• USB B port that is routed through CompactPCI/J5 backplane connector
• EBus B connects to the System Management Controller (SMC) to complete the UltraSPARC host-SMC communication path.

The PCI bus B from the APB connects to a 33 MHz, 32-bit PMC interface on the host board and the SCSI 53C876E from LSI.

The SMC features are:

• The bus arbiter enabling it to control CompactPCI bus arbitration, clock, and reset functions
• The onboard I²C bus, enabling it to communicate with sensors and controls
• The User IPMI bus, enabling user management of other entities in the system. Peripheral hot-swap control is also enabled through this path.

The SMC activates the power module and controls the system reset signals. In addition, it handles high-availability (HA) hot-swap signals from the CompactPCI backplane. For example, ENUM, HEALTHY, BD_SEL, and PCI_RST (the PCI reset signal).