The tables in this chapter describe the relationship between hardware instructions of the SPARC architecture, as defined in The SPARC Architecture Manual and the assembly language instruction set recognized by the SunOS 5.x SPARC assembler.
The SPARC-V9 instruction set is described in Appendix E, SPARC-V9 Instruction Set.
Table 5–1 shows the table notation used in this chapter to describe the instruction set of the assembler. The following notations are commonly suffixed to assembler mnemonics (uppercase letters refer to SPARC architecture instruction names.
Table 5–1
Notations |
Describes |
Comment |
---|---|---|
address |
regrs1 + regrs2 regrs1 + const13 regrs1 – const13 const13 + regrs1 const13 |
Address formed from register contents, immediate constant, or both. |
asi |
|
Alternate address space identifier; an unsigned 8–bit value. It can be the result of the evaluation of a symbol expression. |
const13 |
|
A signed constant which fits in 13 bits. It can be the result of the evaluation of a symbol expression. |
const22 |
|
A constant which fits in 22 bits. It can be the result of the evaluation of a symbol expression. |
creg |
%c0 ... %c31 |
Coprocessor registers. |
freg |
%f0 ... %f31 |
Floating-point registers. |
imm7 |
|
A signed or unsigned constant that can be represented in 7 bits (it is in the range -64 ... 127). It can be the result of the evaluation of a symbol expression. |
reg |
%r0 ... %r31 |
General purpose registers. |
|
%g0 ... %g7 |
Same as %r0 ... %r7 (Globals) |
|
%o0 ... %o7 |
Same as %r8 ... %r15 (Outs) |
|
%l0 ... %l7 |
Same as %r16 ... %r23 (Locals) |
|
%i0 ... %i7 |
Same as %r24 ... %r31 (Ins) |
regrd |
|
Destination register. |
regrs1, regrs2 |
|
Source register 1, source register 2. |
reg_or_imm |
regrs2, const13 |
Value from either a single register, or an immediate constant. |
regaddr |
regrs1 regrs1 + regrs2 |
Address formed with register contents only. |
Software_trap_number |
regrs1 + regrs2 regrs1 + imm7 regrs1 - imm7 uimm7 imm7 + regrs1 |
A value formed from register contents, immediate constant, or both. The resulting value must be in the range 0.....127, inclusive. |
uimm7 |
|
An unsigned constant that can be represented in 7 bits (it is in the range 0 ... 127). It can be the result of the evaluation of a symbol expression. |
The notations described in Table 5–2 are commonly suffixed to assembler mnemonics (uppercase letters for architecture instruction names).
Table 5–2
Notation |
Description |
---|---|
a |
Instructions that deal with alternate space |
b |
Byte instructions |
c |
Reference to coprocessor registers |
d |
Doubleword instructions |
f |
Reference to floating-point registers |
h |
Halfword instructions |
q |
Quadword instructions |
sr |
Status register |
Table 5–3 outlines the correspondence between SPARC hardware integer instructions and SPARC assembly language instructions.
The syntax of individual instructions is designed so that a destination operand (if any), which may be either a register or a reference to a memory location, is always the last operand in a statement.
In Table 5–3,
Braces ({ }) indicate optional arguments.
Braces are not literally coded.
Brackets ([ ]) indicate indirection: the contents of the addressed memory location are being read from or written to.
Brackets are coded literally in the assembly language. Note that the usage of brackets described in Chapter 2, Assembler Syntax differs from the usage of these brackets.
All Bicc and Bfcc instructions described may indicate that the annul bit is to be set by appending ",a" to the opcode mnemonic; for example,
"bgeu,a label"
Table 5–4 shows floating-point instructions. In cases where more than numeric type is involved, each instruction in a group is described; otherwise, only the first member of a group is described.
Table 5–4
All coprocessor-operate (cpopn) instructions take all operands from and return all results to coprocessor registers. The data types supported by the coprocessor are coprocessor-dependent. Operand alignment is also coprocessor-dependent. Coprocessor-operate instructions are described in Table 5–5.
If the EC (PSR_enable_coprocessor) field of the processor state register (PSR) is 0, or if a coprocessor is not present, a cpopn instruction causes a cp_disabled trap.
The conditions that cause a cp_exception trap are coprocessor-dependent.
Table 5–5
SPARC |
Mnemonic |
Argument List |
Name |
Comments |
---|---|---|---|---|
CPop1 |
cpop1 |
opc, regrs1, regrs2, regrd |
Coprocessor operation |
|
CPop2 |
cpop2 |
opc, regrs1, regrs2, regrd |
Coprocessor operation |
May modify ccc |
Table 5–6 describes the mapping of synthetic instructions to hardware instructions.
Table 5–6
Synthetic Instruction |
Hardware Equivalent(s) |
Comment |
||
---|---|---|---|---|
btst |
reg_or_imm, regrs1 |
andcc |
regrs1, reg_or_imm, %g0 |
Bit test |
bset |
reg_or_imm, regrd |
or |
regrd, reg_or_imm, regrd |
Bit set |
bclr |
reg_or_imm, regrd |
andn |
regrd, reg_or_imm, regrd |
Bit clear |
btog |
reg_or_imm, regrd |
xor |
regrd, reg_or_imm, regrd |
Bit toggle |
call |
reg_or_imm |
jmpl |
reg_or_imm, %o7 |
|
clr |
regrd |
or |
%g0, %g0, regrd |
Clear (zero) register |
clrb |
[address] |
stb |
%g0, [address] |
Clear byte |
clrh |
[address] |
st |
%g0, [address] |
Clear halfword |
clr |
[address] |
st |
%g0, [address] |
Clear word |
cmp |
reg, reg_or_imm |
subcc |
regrs1, reg_or_imm, %g0 |
Compare |
dec |
regrd |
sub |
regrd, 1, regrd |
Decrement by 1 |
dec |
const13, regrd |
sub |
regrd, const13, regrd |
Decrement by const13 |
deccc |
regrd |
subcc |
regrd, 1, regrd |
Decrement by 1 and set icc |
deccc |
const13, regrd |
subcc |
regrd, const13, regrd |
Decrement by const13 and set icc |
inc |
regrd |
add |
regrd, 1, regrd |
Increment by 1 |
inc |
const13, regrd |
add |
regrd, const13, regrd |
Increment by const13 |
inccc |
regrd |
addcc |
regrd, 1, regrd |
Increment by 1 and set icc |
inccc |
const13, regrd |
addcc |
regrd, const13, regrd |
Increment by const13 and set icc |
jmp |
address |
jmpl |
address, %g0 |
|
mov mov mov mov mov mov mov mov mov |
reg_or_imm,regrd %y, regrs1 %psr, regrs1 %wim, regrs1 %tbr, regrs1 reg_or_imm, %y reg_or_imm, %psr reg_or_imm, %wim reg_or_imm, %tbr |
or rd rd rd rd wr wr wr wr |
%g0, reg_or_imm, regrd %y, regrs1 %psr, regrs1 %wim, regrs1 %tbr, regrs1 %g0,reg_or_imm,%y %g0,reg_or_imm,%psr %g0,reg_or_imm,%wim %g0,reg_or_imm,%tbr |
|
not |
regrs1, regrd |
xnor |
regrs1, %g0, regrd |
One's complement |
not |
regrd |
xnor |
regrd, %g0, regrd |
One's complement |
neg |
regrs1, regrd |
sub |
%g0, regrs2, regrd |
Two's complement |
neg |
regrd |
sub |
%g0, regrd, regrd |
Two's complement |
restore |
|
restore |
%g0, %g0, %g0 |
Trivial restore |
save |
|
save |
%g0, %g0, %g0 |
Trivial save trivial save should only be used in supervisor code! |
set |
value,regrd |
or |
%g0, value, regrd |
if -4096 ≤value ≤ 4095 Do not use the set synthetic instruction in an instruction delay slot. |
set |
value,regrd |
sethi |
%hi(value), regrd |
if ((value & 0x3ff) == 0) |
set |
value, regrd |
sethi or |
%hi(value), regrd; regrd, %lo(value), regrd |
otherwise Do not use the set synthetic instruction in an instruction delay slot. |
skipz |
|
bnz,a .+8 |
|
if z is set, ignores next instruction |
skipnz |
|
bz,a .+8 |
|
if z is not set, ignores next instruction |
tst |
reg |
orcc |
regrs1, %g0, %g0 |
test |
Table 5–7 describes the V8/V9 natural pseudo instructions that will help increase the portability of your assembly code from V8/V8plus to V9.
Table 5–7
Pseudo Instructions |
-xarch= |
|
---|---|---|
V9 |
||
ldn |
ld |
ldx |
stn |
st |
stx |
ldna |
lda |
ldxa |
stna |
sta |
stxa |
setn |
set |
setx |
setnhi |
sethi |
setxhi |
casn |
cas |
casx |
slln |
sll |
sllx |
srln |
srl |
srlx |
sran |
sra |
srax |
clrn |
clr |
clrx |
Depending on the value set for the -xarch option, the assembler substitutes the appropriate pseudo instruction.