C H A P T E R 2 - PCI FCode Information

C H A P T E R 2

PCI FCode Information

This chapter contains basic information for developers writing FCode for use with PCI. It includes the following sections:

PCI FCode PROM Header Format

The PCI Expansion PROM Header Format

PCI Expansion PROM Data Structure Format

Format of Physical Address in reg Property

CPU PROM-Generated Properties

Adding a PCI Header to a PROM

PCI FCode PROM Header Format

The PCI FCode PROM header format is as follows:

TABLE 2-1 PCI FCode PROM Header Format
Header	Format
`a.out` header	32 bytes (needed by some utilities)
PCI expansion PROM header	28 bytes
PCI data structure	24 bytes
FCode	(8 Byte FCode header + FCode code bytes)

The a.out header is required in order to download an FCode image using dload or boot on a Solaris trademark 1.x (SunOS 4.x) system if, for instance, during test/development of your FCode driver, you don't want to use a physical PROM.

If you use dload or boot to put your FCode image on a system with a Solaris 2.x operating environment, you must replace the a.out header with an ELF header.

The fakeboot utility can add either an a.out or an ELF header based on parameters that you pass to fakeboot.

The PCI Expansion PROM Header Format

The PCI expansion PROM header format (28 bytes) is as follows:

TABLE 2-2 PCI Expansion PROM Header Format
Byte Offset	Value (hexidecimal)	Description
00	55(h)	PROM signature byte one
01	aa(h)	PROM signature byte two
02-03	34 00(h)	SPARC reserved value
04-17	00 00	Reserved for processor architecture-unique data
18-19	1c 00	Pointer to PCI data structure (assuming PCI data structure follows immediately after PCI expansion PROM header)
1A-1B	00 00	Pad bytes

PCI Expansion PROM Data Structure Format

The PCI expansion PROM data structure format (24 bytes) is as follows:

TABLE 2-3 PCI Expansion PROM Data Structure Format
Byte Offset	Description/(Hex. value)
00-03	Signature : P C I R (50 43 49 52)
04-05	Vendor ID
06-07	Device ID
08-09	Pointer to vital product data
0A-0B	PCI data structure length (18 00)
0C	PCI data structure revision
0D	Programming interface code
0E	Subclass code
0F	Class code
10-11	Image length in 512 bytes
12-13	Revision level of code/data
14	Code type (01)
15	Indicator byte. For last image (80)
16-17	Reserved (00 00)

The following is a dump of initial bytes in a PCI FCode PROM with an a.out header in the first 32 bytes.

TABLE 2-4 PCI FCode PROM Dump
`00000`	`01 03 01 07 00 00 46 98 00 00 00 00 00 00 00 00`
`00010`	`00 00 00 00 00 00 40 00 00 00 00 00 00 00 00 00`
`00020`	`55 aa 34 00 00 00 00 00 00 00 00 00 00 00 00 00`
`00030`	`00 00 00 00 00 00 00 00 1c 00 00 00 50 43 49 52`
`00040`	`8e 10 01 10 00 c0 18 00 00 00 00 02 7e 00 00 01`
`00050`	`01 80 00 00 f1 03 18 6e 00 00 46 64 xx xx xx xx`

For the PROM above, the vendor ID is 0x108e, the device ID is 0x1001, the pointer to Vital Product Data is 0xc000, the class code is 0x02, the subclass code is 0, the programming interface code is 0, the image length (in 512 bytes) is 0x7e, the FCode length is 0x4664 bytes, and the xx are FCode data.

Format of Physical Address in `reg` Property

For PCI, the "reg" property value has five 32-bit numbers: phys.hi, phys.mid, phys.lo, size.hi, and size.lo. The size.hi and size.lo are values for a register size of which the address and type are defined by phys.hi, phys.mid, and phys.low.

The format of the physical address in the reg property is as follows:

TABLE 2-5 Format of Physical Address in `reg` Property
`phys.hi cell:`	`npt000ss bbbbbbbb dddddfff rrrrrrrr`
`phys.mid cell:`	`hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh`
`phys.low cell:`	`LLLLLLLL LLLLLLLL LLLLLLLL LLLLLLLL`

where

n is 0 if the address is relocatable; 1 otherwise.

p is 1 if the addressable region is prefetchable; 0 otherwise.

t is 1 if the address is aliased (for non-relocatable I/O), below 1 Mbyte (for memory), or below 64 Kbytes (for relocatable I/O).

ss=00 ==> configuration space

ss=01 ==> I/O space

ss=10 ==> 32-bit memory space

ss=11 ==> 64-bit memory space

bbbbbbbb is an 8-bit bus number (assigned by the CPU PROM at probe time).

ddddd is a 5-bit device number.

fff is a 3-bit function number.

rrrrrrrr is an 8-bit register number.

hh..hh is a 32-bit unsigned number, most significant bits.

LL..LL is a 32-bit unsigned number, least significant bits.

CPU PROM-Generated Properties

This section describes the properties created by the motherboard CPU PROM from the information in the configuration space registers of the PCI device.

The CPU PROM normally generates the following properties in a PCI device node:

vendor-id

device-id

revision-id

class-code

It also generates devsel-speed from the information in the configuration space registers. The interrupts property is present if the Interrupt Pin register is nonzero. The following properties are present only if the corresponding capability is available from the device or if the corresponding value was nonzero as indicated in the configuration space registers:

66mhz-capable

udf-supported

cache-line-size

fast-back-to-back

subsystem-id

subsystem-vendor-id

The min-grant and max-latency properties are created unless the header type is 01. The CPU PROM also creates the assigned-addresses property, with entries for each address base register for which an address is assigned.

Adding a PCI Header to a PROM

You can see an example in test-pci.fth or add a PCI header using the following example:

tokenizer[

\ to add vendor id, device id and class code

h# 108e h# 1001 h# 020000 pci-header

\ to add vital product data

h# c000 pci-vpd-offset

\ to add pci-code-revision

h# 1234 pci-code-revision

]tokenizer

fcode-version3

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