Features Tables

Power consumption 

P=VI 

25W (5V x 5A) 

None 

Power supply 

5V +/-.25V 2A max per connector 

12V +/-.75V 30mA max per connector 

5V +/-5% 5A max per connector 

3.3V +/-.3V & .6A max per connector 

12V +/-5% 500ma per connector 

-12V +/-10% 100ma per connector 

None 

FCode required 

All devices 

Boot and console devices 

None 

Address allocation 

Static mapping. Slot has known start address and length 

Dynamic mapping for I/O and memory address spaces. Slot distinguished only by address of configuration space header. 

None 

Addressing mode 

Use virtual addressing. Require MMU in SBus controller and address translation. 

32-bit virtual address for masters, 

28-bit physical address space per slave. 

Normal address mode 

None 

Address spaces 

Standard chunk of memory-mapped space (28 bits/slot) 

Three physical address spaces: memory, I/O, configuration. 

None 

Auto-configuration 

Burst: 

Transfer mode size 

Available. 

Up to 64 bytes: size declared in advance in SIZ{2:0}. 

Yes 

Variable size, no limit; determined by PCI device and PCI bridge. 

None 

Bus bandwidth: 

(data transfer rate) 

25MHz/32-bit, max. 

100MBytes/sec for 32-bit. 

200 MBytes/sec for 64-bit 

33MHz (rev 2.0) or 66 MHz for  

PCI/66, 32/64bit, maximum rate from 

132MByte/second (33MHz/32-bit) 

to 528MByte/second (66 MHz/64-bit).  

None 

Bus parking 

No 

Yes. An arbiter may grant the busses to a master when the bus is idle and masters are not generating requests for the bus. If the master that the bus is parked on subsequently issues a request from the bus, it can immediately access it. 

None 

Bus width 

x 32-to 64-bit 

Clock frequency/bus speed  

Max CLK 25MHz 

CLK to out: 22nS 

Input Set-up: 15nS 

33MHz max CLK 

CLK to out:22ns 

Input Set-up: 7 ns 

Synchronous; signals referenced to rising clock edge 

Connectors 

One type of connector 

Either 5V or 3.3V 32-and 64-bit connectors; the 64-bit being an extension of the 32-bit 

None 

Data path 

32-bit, except 64-bit for extended transfers 

32/64-bit 

None 

Dynamic Bus Sizing 

Yes. Enables slave to control data width it accepts during non-burst transfers 

No, but same function is performed by Byte Enable setting during Data Phase 

None 

Form factors 

Single form factor per slot (double and triple-wide can share slots) 

Three form factors: short, long, and variable-height short 

None 

Interrupts 

Seven levels 

Four levels (INTA-D) 

None 

Max devices per bus 

Usually limited by electrical loading 

32 slots 

None 

Max functions per device 

1 

8 

None 

Max masters per bus 

8 

32 

None 

Pin count (connector) 

96 

94 pins for both 32-bit and 64-bit connectors 

None 

Parity 

Optional on data and virtual address transfers if parity generation and checking is implemented on controller and installed masters and slaves. 

Default during address and data phases; must be performed by all PCI-compliant devices. 

None 

Address decode 

Slave selected by decode from controller 

Each target performs full 32-bit decoding and drives DEVSEL# if selected 

Burst size 

32 words 

No limit 

Bus driving and turnaround 

None 

A turnaround cycle is necessary for signals driven by more than one agent, to enable contention-avoidance when bus driving agents transfer a signal. 

Byte ordering and placement 

Byte-lane swapping 

DWORD swapping puts bytes in correct lane base on byte address 

Byte ordering 

Big-endian 

Little-endian 

Cycle participants 

Controller, Master, Slave 

PCI Agents: Master/Initiator, Target 

Cycle terminology and composition 

Transfer = 

1. Arbitration Phase 

2. Translation Phase 

3. Extended Transfer Information Phase 

4. Transfer Phase (also called Slave Cycle) 

Transfer = 1 or more clock cycles 

Phase = 1 or more read or write transfers, including (hidden) arbitration while current initiator is performing a data transfer  

Read or write transaction = 1 address phase + 1 or more data phases