Bus Transaction Participants

The bus transaction participants include the SBus controller, PCI arbiter, SBus and PCI masters, and the SBus and PCI targets.

SBus Controller

The SBus controller arbitrates contention between bus masters during the arbitration phase.

The SBus controller also performs the following:

• Address strobe

• Bus arbitration

• Bus time-outs

• Data transfer count

• SBus system clock

• Slave selects

• Virtual address translation and page size restrictions

PCI Arbiter

The PCI arbiter has no true controller but performs functions equivalent to the controller to arbitrate between bus masters. Bus masters can terminate transactions on completion or time-out; targets can also terminate transactions. The arbiter is typically integrated into the host/PCI or the PCI/expansion bus bridge chip.

SBus Master

The SBus master controls operations that produce error-free data read and write tasks between itself and an SBus slave.

The master-initiated transaction types are:

• Arbitration

• Translation

• Default transfer

• Extended transfer

PCI Master

The PCI master becomes an initiator when it has arbitrated for and gained access to the PCI bus. The initiator starts transfers but can also abort, terminate, and time out.

The master also does the following:

• Starts the Address Phase

• Inserts wait states during data transfer

• Terminates transactions

SBus Slave/Target

The SBus slave/target performs as follows:

• Monitors the SBus to determine if a master is requesting a data transfer

• Provides the data requested to the SBus master during the transfer phase

• Does not perform address decoding; the master does this

• Participates in burst transfers, dynamic bus-sizing, extended transfer phases

• Controls the data transfer rate by controlling the data acknowledgment rate

• Terminates transactions

PCI Target

The PCI target performs the following functions:

• Determines that it is the target of a transaction

• Receives a data object from the initiator

• Decodes addresses

• Participates in special cycles

• Inserts wait states during data transfer (controls data transfer rate)

• Terminates transactions