Protocol

Protocol contains the SBus and PCI basic transaction cycles for each bus, and bus arbitration.

SBus Basic Cycles

The following are definitions of the SBus basic transaction cycle for each bus.

Arbitration Phase--During this phase, masters request bus access. When there is contention between masters, the controller determines which master performs the next transfer. After arbitration, the controller is responsible for monitoring the transfer.

Translation Phase--The master and controller participate in conversion of the virtual addresses to physical address and selection signals that are used by the master and the slaves.

Extended Transfer Information Phase--This phase is used only for the cycles requested by the master that have a SIZ[2:0] value of Extended Transfer.

Transfer Phase--During the Transfer Phase (slave cycle), data is moved to or from the slave.

Dynamic Bus-sizing--This feature enables a master to communicate more easily with slaves of varying widths.

Burst Transfers--SBus burst transfer protocol is the same as that for SBus basic transactions, except that multiple words are transferred. Neither dynamic bus-sizing or varying-width slaves are allowed.

Extended Transfer Mode--These 64-bit transfers enable increased performance. Up to twice the bandwidth is possible, as the data path is twice as wide.

PCI Basic Cycles

The following are definitions of the PCI basic transaction cycle for each bus.

Address Phase--Every PCI transaction begins with this phase, which includes concurrent hidden arbitration.

The initiator identifies the target device and transaction type.

Data Phase--At the end of the address phase, the address/data bus transfers data in one or more data phases. The clock immediately following the Address Phase begins the data phase.

During the data phase, a data object is transferred between initiator and target during every rising edge of the PCI bus clock.

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Note -

Bus Idle State - When the last data transfer has finished, the initiator returns the bus to the idle state, which is the condition of having no transaction in progress on the bus.

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Bus Arbitration

Bus arbitration by the SBus enables concurrent arbitration and transfer execution. The PCI arbitration is access-based, not time-slot-based, to minimize access latency.

SBus

When more than one SBus master requests bus access, the controller grants access to one of the requesters. Enabling arbitration concurrent while the master makes a data transfer referred to as hidden arbitration.

PCI

In PCI arbitration, a bus master must arbitrate for each bus access.

The PCI specification does not define the PCI bus arbitration scheme. The arbiter may use any scheme, but the 2.1 specification requires that the arbiter implement a fairness algorithm to avoid deadlocks.