Latency

SBus and PCI bus latency characteristics are similar. Both are low-latency, high-throughput buses. The number of wait states that targets and masters can add to a transaction is limited. Also, masters have programmable timers that limit their times on the bus during heavy-traffic periods. The limits, plus bus arbitration order, ensure that bus acquisition latencies can accurately be predicted for any bus master.

PCI and SBus latencies are functions of:

• The number of bus masters

• The arbitration method and its overhead time

• The length of an SBus translation phase or a PCI data phase

• The time the slave or target takes to finish the transfer

• The occurrence of retries and errors.

Bus access latency is the elapsed time from the moment that a bus master requests bus access until it finishes the first data transfer of the transaction. Table 6 describes the bus access latency components.

Table 1-6 PCI Bus Access Latency Components

Component	Description
Bus access latency	The elapsed time from the moment a master requests bus access until it finishes the transactions's first data transfer
Arbitration latency	The time that the master issues a request to the time when the arbiter asserts the master's grant
Bus acquisition latency	The elapsed time that the requesting master receives the grant until the current master surrenders the bus
Target latency	The elapsed time that transaction starts until the currently-addressed target is ready to finish the transactions's first data transfer

PCI Bridge Information