Writing FCode 3.x Programs
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This chapter contains basic information for developers writing FCode for use with PCI. It includes the following sections:
PCI FCode PROM Header Format
The PCI FCode PROM header format is as follows:
TABLE 2-1 PCI FCode PROM Header Format
Header
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Format
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a.out header
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32 bytes (needed by some utilities)
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PCI expansion PROM header
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28 bytes
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PCI data structure
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24 bytes
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FCode
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(8 Byte FCode header + FCode code bytes)
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The a.out header is required in order to download an FCode image using dload or boot on a Solaris 1.x (SunOS 4.x) system if, for instance, during test/development of your FCode driver, you don't want to use a physical PROM.
If you use dload or boot to put your FCode image on a system with a Solaris 2.x operating environment, you must replace the a.out header with an ELF header.
The fakeboot utility can add either an a.out or an ELF header based on parameters that you pass to fakeboot.
The PCI Expansion PROM Header Format
The PCI expansion PROM header format (28 bytes) is as follows:
TABLE 2-2 PCI Expansion PROM Header Format
Byte Offset
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Value (hexidecimal)
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Description
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00
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55(h)
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PROM signature byte one
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01
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aa(h)
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PROM signature byte two
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02-03
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34 00(h)
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SPARC reserved value
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04-17
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00 00
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Reserved for processor architecture-unique data
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18-19
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1c 00
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Pointer to PCI data structure (assuming PCI data structure follows immediately after PCI expansion PROM header)
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1A-1B
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00 00
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Pad bytes
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PCI Expansion PROM Data Structure Format
The PCI expansion PROM data structure format (24 bytes) is as follows:
TABLE 2-3 PCI Expansion PROM Data Structure Format
Byte Offset
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Description/(Hex. value)
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00-03
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Signature : P C I R (50 43 49 52)
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04-05
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Vendor ID
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06-07
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Device ID
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08-09
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Pointer to vital product data
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0A-0B
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PCI data structure length (18 00)
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0C
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PCI data structure revision
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0D
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Programming interface code
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0E
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Subclass code
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0F
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Class code
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10-11
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Image length in 512 bytes
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12-13
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Revision level of code/data
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14
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Code type (01)
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15
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Indicator byte. For last image (80)
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16-17
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Reserved (00 00)
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The following is a dump of initial bytes in a PCI FCode PROM with an a.out header in the first 32 bytes.
TABLE 2-4 PCI FCode PROM Dump
00000
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01 03 01 07 00 00 46 98 00 00 00 00 00 00 00 00
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00010
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00 00 00 00 00 00 40 00 00 00 00 00 00 00 00 00
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00020
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55 aa 34 00 00 00 00 00 00 00 00 00 00 00 00 00
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00030
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00 00 00 00 00 00 00 00 1c 00 00 00 50 43 49 52
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00040
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8e 10 01 10 00 c0 18 00 00 00 00 02 7e 00 00 01
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00050
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01 80 00 00 f1 03 18 6e 00 00 46 64 xx xx xx xx
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For the PROM above, the vendor ID is 0x108e, the device ID is 0x1001, the pointer to Vital Product Data is 0xc000, the class code is 0x02, the subclass code is 0, the programming interface code is 0, the image length (in 512 bytes) is 0x7e, the FCode length is 0x4664 bytes, and the xx are FCode data.
Format of Physical Address in reg Property
For PCI, the "reg" property value has five 32-bit numbers: phys.hi, phys.mid, phys.lo, size.hi, and size.lo. The size.hi and size.lo are values for a register size of which the address and type are defined by phys.hi, phys.mid, and phys.low.
The format of the physical address in the reg property is as follows:
TABLE 2-5 Format of Physical Address in reg Property
phys.hi cell:
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npt000ss bbbbbbbb dddddfff rrrrrrrr
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phys.mid cell:
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hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh
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phys.low cell:
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LLLLLLLL LLLLLLLL LLLLLLLL LLLLLLLL
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where
- n is 0 if the address is relocatable; 1 otherwise.
- p is 1 if the addressable region is prefetchable; 0 otherwise.
- t is 1 if the address is aliased (for non-relocatable I/O), below 1 Mbyte (for memory), or below 64 Kbytes (for relocatable I/O).
- ss=00 ==> configuration space
- ss=01 ==> I/O space
- ss=10 ==> 32-bit memory space
- ss=11 ==> 64-bit memory space
- bbbbbbbb is an 8-bit bus number (assigned by the CPU PROM at probe time).
- ddddd is a 5-bit device number.
- fff is a 3-bit function number.
- rrrrrrrr is an 8-bit register number.
- hh..hh is a 32-bit unsigned number, most significant bits.
- LL..LL is a 32-bit unsigned number, least significant bits.
CPU PROM-Generated Properties
This section describes the properties created by the motherboard CPU PROM from the information in the configuration space registers of the PCI device.
The CPU PROM normally generates the following properties in a PCI device node:
- vendor-id
- device-id
- revision-id
- class-code
It also generates devsel-speed from the information in the configuration space registers. The interrupts property is present if the Interrupt Pin register is nonzero. The following properties are present only if the corresponding capability is available from the device or if the corresponding value was nonzero as indicated in the configuration space registers:
- 66mhz-capable
- udf-supported
- cache-line-size
- fast-back-to-back
- subsystem-id
- subsystem-vendor-id
The min-grant and max-latency properties are created unless the header type is 01. The CPU PROM also creates the assigned-addresses property, with entries for each address base register for which an address is assigned.
Adding a PCI Header to a PROM
You can see an example in test-pci.fth or add a PCI header using the following example:
tokenizer[
\ to add vendor id, device id and class code
h# 108e h# 1001 h# 020000 pci-header
\ to add vital product data
h# c000 pci-vpd-offset
\ to add pci-code-revision
h# 1234 pci-code-revision
]tokenizer
fcode-version3
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end0
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Writing FCode 3.x Programs
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806-1379-10
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Copyright © 2004, Sun Microsystems, Inc. All Rights Reserved.