ADD
|
add
|
regrs1, reg_or_imm, regrd
|
Add
|
|
ADDcc
|
addcc
|
regrs1, reg_or_imm, regrd
|
Add and modify icc
|
|
ADDX
|
addx
|
regrs1, reg_or_imm, regrd
|
Add with carry
| |
ADDXcc
|
addxcc
|
regrs1, reg_or_imm, regrd
|
|
|
AND
|
and
|
regrs1, reg_or_imm, regrd
|
And
| |
ANDcc
|
andcc
|
regrs1, reg_or_imm, regrd
| |
|
ANDcc
|
andn
|
regrs1, reg_or_imm, regrd
| |
|
ANDNcc
|
andcc
|
regrs1, reg_or_imm, regrd
| |
|
BN
|
bn{,a}
|
label
|
Branch on integer condition codes
|
branch never
|
BNE
|
bne{,a}
|
label
|
|
synonym: bnz
|
BE
BG
BLE
BGE
BI
BGU
BLEU
|
be{,a}
bg{,a}
ble{,a}
bge{,a}
bl{,a}
bgu{,a}
bleu{,a}
|
label
label
label
label
label
label
label
|
|
synonym: bz
|
BCC
|
bcc{,a}
|
label
|
|
synonym: bgeu
|
BCS
BPOS
BNEG
BVC
BVS
|
bcs{,a}
bpos{,a}
bneg{,a}
bvc{,a}
bvs{,a}
|
label
label
label
label
label
|
|
synonym: blu
|
BA
|
ba{,a}
|
label
|
|
synonym: b
|
CALL
|
call
|
label
|
Call subprogram
|
|
CBccc
|
cbn{,a}
cb3{,a}
cb2{,a}
cb23{,a}
cb1{,a}
cb13{,eo}
cb12{,a}
cb123{,a}
cb0{,a}
cb03{,a}
cb02{,a}
cb023{,a}
cb01{,a}
cb013{,a}
cb012{,a}
cba{,a}
|
label
label
label
label
label
label
label
label
label
label
label
label
label
label
label
label
|
Branch on coprocessor condition codes
|
branch never
|
FBN
FBU
FBG
FBUG
FBL
FBUL
FBLG
|
fbn{,a}
fbu{,a}
fbg{,a}
fbug{,a}
fbl{,a}
fbul{,a}
fblg{,a}
|
label
label
label
label
label
label
label
|
Branch
on floating-point condition codes
|
branch never
|
FBNE
|
fbne{,a}
|
label
|
|
synonym: fbnz
|
FBE
|
fbe{,a}
|
label
|
|
synonym: fbz
|
FBUE
FBGE
FBUGE
FBLE
FBULE
FBO
FBA
|
fbue{,a}
fbge{,a}
fbuge{,a}
fble{,a}
fbule{,a}
fbo{,a}
fba{,a}
|
label
label
label
label
label
label
label
|
|
|
FLUSH
|
flush
|
address
|
Instruction cache flush
|
|
JMPL
|
jmpl
|
address, regrd
|
Jump and link
|
|
LDSB
|
ldsb
|
[address], regrd
|
Load signed
byte
|
|
LDSH
|
ldsh
|
[address], regrd
|
Load signed halfword
|
|
LDSTUB
|
ldstub
|
[address], regrd
|
Load-store unsigned byte
|
|
LDUB
|
ldub
|
[address], regrd
|
Load unsigned byte
|
|
LDUH
|
lduh
|
[address], regrd
|
Load unsigned halfword
|
|
LD
|
ld
|
[address], regrd
|
Load
word
|
|
LDD
|
ldd
|
[address], regrd
|
Load double word
|
regrd must be even
|
LDF
|
ld
|
[address], fregrd
|
|
|
LDFSR
|
ld
|
[address], %fsr
|
Load
floating-point register
|
|
LDDF
|
ldd
|
[address], fregrd
|
Load double floating-point
|
fregrd must be even
|
LDC
|
ld
|
[address], cregrd
|
Load coprocessor
|
|
LDCSR
|
ld
|
[address], %csr
|
Load
double coprocessor
|
|
LDDC
|
ldd
|
[address], cregrd
|
|
|
LDSBA
LDSHA
LDUBA
LDUHA
LDA
|
ldsba
ldsha
lduba
lduha
lda
|
[regaddr]asi, regrd
[regaddr]asi, regrd
[regaddr]asi, regrd
[regaddr]asi, regrd
[regaddr]asi, regrd
|
Load signed byte from alternate space
|
|
LDDA
|
ldda
|
[regaddr]asi, regrd
|
|
regrd must be even
|
LDSTUBA
|
ldstuba
|
[regaddr]asi, regrd
|
|
|
MULScc
|
mulscc
|
regrs1, reg_or_imm, regrd
|
Multiply step (and modify icc)
|
|
NOP
|
nop
|
|
No operation
|
|
OR
ORcc
ORN
ORNcc
|
or
orcc
orn
orncc
|
regrs1, reg_or_imm, regrd
regrs1, reg_or_imm, regrd
regrs1, reg_or_imm, regrd
regrs1, reg_or_imm, regrd
|
Inclusive or
|
|
RDASR
|
rd
|
%asrnrs1, regrd
|
|
|
RDY
|
rd
|
%y, regrd
|
|
See synthetic instructions.
|
RDPSR
|
rd
|
%psr,
regrd
|
|
See synthetic instructions.
|
RDWIM
|
rd
|
%wim,
regrd
|
|
See synthetic instructions.
|
RDTBR
|
rd
|
%tbr,
regrd
|
|
See synthetic instructions.
|
RESTORE
|
restore
|
regrs1, reg_or_imm, reg rd
|
|
See synthetic instructions.
|
RETT
|
rett
|
address
|
Return from trap
|
|
SAVE
|
save
|
regrs1, reg_or_imm, regrd
|
|
See synthetic instructions.
|
SDIV
|
sdiv
|
regrs1, reg_or_imm, regrd
|
Signed divide
|
|
SDIVcc
|
sdivcc
|
regrs1, reg_or_imm, regrd
|
Signed divide and modify icc
|
|
SMUL
|
smul
|
regrs1, reg_or_imm, regrd
|
Signed multiply
|
|
SMULcc
|
smulcc
|
regrs1, reg_or_imm, regrd
|
Signed multiply and modify icc
|
|
SETHI
|
sethi
|
const22, regrd
|
Set
high 22 bits of register
|
|
|
sethi
|
%hi(value), regrd
|
|
See synthetic instructions.
|
SLL
|
sll
|
regrs1, reg_or_imm, regrd
|
Shift left logical
|
|
SRL
|
srl
|
regrs1, reg_or_imm, regrd
|
Shift right logical
|
|
SRA
|
sra
|
regrs1, reg_or_imm, regrd
|
Shift right arithmetic
|
|
STB
|
stb
|
regrd, [address]
|
Store byte
|
Synonyms: stub, stsb
|
STH
|
sth
|
regrd, [address]
|
Store half-word
|
Synonyms: stuh, stsh
|
ST
|
st
|
regrd, [address]
|
|
|
STD
|
std
|
regrd, [address]
|
|
regrd Must be even
|
STF
|
st
|
fregrd, [address]
|
|
|
STDF
|
std
|
fregrd, [address]
|
|
|
STFSR
|
st
|
%fsr, [address]
|
Store floating-point status register
|
fregrd Must be even
|
STDFQ
|
std
|
%fq, [address]
|
Store double floating-point queue
|
|
STC
|
st
|
cregrd, [address]
|
Store coprocessor
|
cregrd Must be even
|
STDC
|
std
|
cregrd, [address]
|
|
cregrd Must be even
|
STCSR
|
st
|
%csr,
[address]
|
|
|
STDCQ
|
std
|
%cq, [address]
|
Store double
coprocessor
|
|
STBA
|
stba
|
regrd [regaddr]asi
|
Store byte into alternate space
|
Synonyms: stuba, stsba
|
STHA
|
stha
|
regrd [regaddr]asi
|
|
Synonyms: stuha, stsha
|
STA
|
sta
|
regrd, [regaddr]asi
|
|
|
STDA
|
stda
|
regrd, [regaddr]asi
|
|
regrd Must be even
|
SUB
|
sub
|
regrs1, reg_or_imm, regrd
|
Subtract
|
|
SUBcc
|
subcc
|
regrs1, reg_or_imm, regrd
|
Subtract and modify icc
|
|
SUBX
|
subx
|
regrs1, reg_or_imm, regrd
|
Subtract with carry
|
|
SUBXcc
|
subxcc
|
regrs1, reg_or_imm, regrd
|
|
|
SWAP
SWAPA
|
swap
swapa
|
[address], regrd
[regaddr]asi, regrd
|
Swap memory word
with register
|
|
Ticc
|
tn
|
software_trap_number
|
Trap on integer condition code
|
Trap never
|
|
tne
|
software_trap_number
|
Note: Trap numbers 16-31 are reserved
for the user. Currently-defined trap numbers are those defined in /usr/include/sys/trap.h
|
Synonym: tnz
|
|
te
tg
tle
tge
tl
tgu
|
software_trap_number
software_trap_number
software_trap_number
software_trap_number
software_trap_number
software_trap_number
|
|
Synonym: tz
|
|
tleu
|
software_trap_number
|
|
Synonym: tcc
|
|
tlu
tgeu
tpos
tneg
|
software_trap_number
software_trap_number
software_trap_number
software_trap_number
|
|
Synonym: tcc
|
|
tvc
tvs
ta
|
software_trap_number
software_trap_number
software_trap_number
|
|
Synonym: t
|
TADDcc
TSUBcc
|
taddcc
tsubcc
|
regrs1, reg_or_imm, regrd
regrs1, reg_or_imm, regrd
|
Tagged
add and modify icc
|
|
TADDccTV
TSUBccTV
|
taddcctv
tsubcctv
|
regrs1, reg_or_imm, regrd
regrs1, reg_or_imm, regrd
|
Tagged
add and modify icc and trap on overflow
|
|
UDIV
|
udiv
|
regrs1, reg_or_imm, regrd
|
Unsigned divide
|
|
UDIVcc
|
udivcc
|
regrs1, reg_or_imm, regrd
|
Unsigned divide and modify icc
|
|
UMUL
|
umul
|
regrs1, reg_or_imm, regrd
|
Unsigned multiply
|
|
UMULcc
|
umulcc
|
regrs1, reg_or_imm, regrd
|
Unsigned multiply and modify icc
|
|
UNIMP
|
unimp
|
const22
|
Illegal instruction
|
|
WRASR
|
wr
|
reg_or_imm, %asrnrs1
|
|
|
WRY
|
wr
|
regrs1, reg_or_imm, %y
|
|
See synthetic instructions
|
WRPSR
|
wr
|
regrs1, reg_or_imm, %psr
|
|
See synthetic instructions
|
WRWIM
|
wr
|
regrs1, reg_or_imm, %wim
|
|
See synthetic instructions
|
WRTBR
|
wr
|
regrs1, reg_or_imm, %tbr
|
|
See synthetic instructions
|
XNOR
XNORcc
|
xnor
xnorcc
|
regrs1, reg_or_imm, regrd
regrs1, reg_or_imm, regrd
|
Exclusive nor
|
|
XOR
XORcc
|
xor
xorcc
|
regrs1, reg_or_imm, regrd
regrs1, reg_or_imm, regrd
|
Exclusive or
|
|