Glossary

B

This glossary lists terms and acronyms used in this manual.

ASIC

Application-specific integrated circuit.

C30

A digital signal processor, specifically a TMS320C30, used on the Graphics Processor Rendering Pipeline board.

CLUT

Color look-up table.

DAC

Digital-to-analog converter.

DRAM

Dynamic Random Access Memory.

DSP

Digital signal processor.

Edge Walker

An ASIC on the Graphics Processor Rendering Pipeline board that interpolates down triangle edges, generating information for each scan line on which the Span Interpolator can operate.

EMI

Electro-magnetic interference.

EW

Edge Walker.

FB

Frame Buffer board.

FBI

Frame Buffer input.

FBO

Frame Buffer output.

FIFO

First-in first-out buffer.

FRU

Field-replaceable unit.

GPFE

Graphics Processor Front End board.

GPRP

Graphics Processor Rendering Pipeline board.

HAC

Host adapter cable.

HSA

Host SBus adapter board - now the GT SBus Adapter board.

Host adapter cable

The interface cable between the GT SBus Adapter board in the system unit and the Graphics Processor Front End board in the Graphics Tower.

i860

A microprocessor known as the front end processor on the Graphics Processor Front End board. The i860 performs pre-processing of acceleration commands prior to sending intermediate commands to the Setup Processor for additional processing.

LDM

Local Data Memory.

Local Data Bus

A bus that connects the Graphics Processor Front End board with the Graphics Processor Rendering Pipeline board.

Local Data Memory

A 2M-byte fast-page mode DRAM on the Graphics Processor Front End board, which provides both i860 data store and i860 instruction code.

MIA

Moonshine Interface ASIC.

Moonshine Interface ASIC

An ASIC on the Graphics Processor Front End board that performs virtual memory mapping, fetches data from the system unit memory and caches the data for presentation to the Front End Processor.

PB

Pixel Bus.

PF

Pixel Formatter.

Pixel Formatter

An ASIC on the Frame Buffer board that handles the extension of complex Pixel Bus requests into one-pixel-per-cycle accesses to the Frame Buffer.

Pixel Processor

An ASIC on the Frame Buffer board that handles all one-pixel-per-cycle accesses to the Frame Buffer.

PP

Pixel Processor.

RAMDAC

A digital-to-analog convert with built-in RAM-based lookup tables.

Setup Processor

An ASIC on the Graphics Processor Rendering Pipeline board that converts vector and triangle chains into separate vectors and triangles and computes slopes for all pertinent parameters.

SI

Span Interpolator.

Span Interpolator

An ASIC on the Graphics Processor Rendering Pipeline board that steps pixel- by-pixel across a triangle span or along a vector, performing all the per-pixel interpolations.

SU

Setup Processor.

Video Memory Array

A memory plane on the Frame Buffer board that contains the Frame Buffer storage planes.

VMA

Video Memory Array.

WID LUT

Window ID look-up table.