Introduction to Sun WorkShop

Appendix B

The make Utility and Makefiles

You can use the make utility and makefiles to help automate building of an application with Sun WorkShop. This appendix provides some basic information about the make utility, makefiles, and makefile macros. It also refers you to dialog boxes in Sun WorkShop that allow you to set makefile options and to add, delete, and override makefile macros. To build your programs without writing your own makefile, see Building a Program and Building With Default Values.

The make utility applies intelligence to the task of program compilation and linking. Typically, a large application might exist as a set of source files and INCLUDE files, which require linking with a number of libraries. Modifying any one or more of the source files requires recompilation of that part of the program and relinking. You can automate this process by specifying the interdependencies between files that make up the application along with the commands needed to recompile and relink each piece. With these specifications in a file of directives, make insures that only the files that need recompiling are recompiled and that relinking uses the options and libraries you want.

For more information, there are commercially published books on how to use make as a program development tool, including Managing Projects with make, by Oram and Talbott, from O'Reilly & Associates.

The Makefile

A file called makefile tells the make utility in a structured manner which source and object files depend on other files. It also defines the commands required to compile and link the files.

Each file to build, or step to perform, is called a target. Each entry in a makefile is a rule expressing a target object's dependencies and the commands needed to build or make that object. The structure of a rule in the makefile is:

target: dependencies-list TAB build-commands

For the dependencies, each entry starts with a line that names the target file, followed by all the files the target depends on. For the build commands, each entry has one or more subsequent lines that specify the Bourne shell commands that will build the target file for this entry. Each of these command lines must be indented by a tab character.

Fortran 77 Example

You have a program consisting of the following source files and a makefile:

• makefile
• commonblock
• computepts.f
• pattern.f
• startupcore.f

Both pattern.f and computepts.f have an INCLUDE of commonblock, and you wish to compile each .f file and link the three relocatable files, along with a series of libraries, into a program called pattern.

The makefile contains the following lines.

CODE EXAMPLE B-1 Fortran 77 Makefile

pattern: pattern.o computepts.o startupcore.o f77 pattern.o computepts.o startupcore.o -lcore77 \ -lcore -lsunwindow -lpixrect -o pattern pattern.o: pattern.f commonblock f77 -c -u pattern.f computepts.o: computepts.f commonblock f77 -c -u computepts.f startupcore.o: startupcore.f f77 -c -u startupcore.f

The first line of this makefile indicates that making pattern depends on pattern.o, computepts.o, and startupcore.o. The next line and its continuations give the command for making pattern from the relocatable.o files and libraries.

C++ Example

You have a program consisting of the following source files and a makefile:

• manythreads.cc
• Makefilemany.cc
• thr.cc
• misc.h
• defines.h

The target files are:

• many
• manythreads
• thrI

The makefile contains the following lines.

CODE EXAMPLE B-2 C++ Makefile

all: many manythreads thrI many: many.cc CC -o many many.cc -g -D_REENTRANT -lm -lnsl -lsocket -lthread thrI: thr.cc CC -o thrI thr.cc -g -D_REENTRANT -lm -lnsl -lsocket -lthread manythreads: manythreads.cc CC -o manythreads -g -D_REENTRANT manythreads.cc -lnsl \ -lsocket -lthread

The first line of this makefile groups a set of targets with the label all. The succeeding lines give the commands for making the three targets, each of which has a dependency on one of the source files.

The make Utility

To start the make utility, type the following at a command line:

% make

You can add a number of options to the make command for your application using the Build Options dialog box in Sun WorkShop (see Specifying Build Options).

The make utility looks for a file named makefile or Makefile in the current directory and takes its instructions from that file.

The make utility:

1. Reads makefile to determine all the target files it must process, the files they depend on, and the commands needed to build them

2. Finds the date and time each file was last changed

3. Rebuilds any target file that is older than any of the files it depends on, using the commands from makefile for that target

To make writing a makefile easier, the make utility has default rules that it uses depending on the suffix of a target file. Recognizing the .f suffix, make uses the f77 compiler, passing as arguments any flags specified by the FFLAGS macro, the -c flag, and the name of the source file to be compiled.

CODE EXAMPLE B-3 demonstrates this rule twice.

CODE EXAMPLE B-3 make Default

OBJ = pattern.o computepts.o startupcore.o FFLAGS=-u pattern: $(OBJ) f77 $(OBJ) -lcore77 -lcore -lsunwindow \ -lpixrect -o pattern pattern.o: pattern.f commonblock f77 $(FFLAGS) -c pattern.f computepts.o: computepts.f commonblock startupcore.o: startupcore.f

Suffix Rule

make uses default rules to compile computepts.f and startupcore.f. Similarly, the suffix rules for .f95 files invoke the f95 compiler.

Macros

The make utility's macro facility allows simple parameterless string substitutions. For example, the list of relocatable files that make up the target program pattern can be expressed as a single macro string, making it easier to change. See also the make(1S) man page for information about make macros.

A macro string definition has the form:

% make NAME=string

Use of a macro string is indicated by $(NAME), which is replaced by make with the actual value of the macro string named.

This example adds a macro definition naming all the object files to the beginning of makefile:

OBJ=pattern.o computepts.o startupcore.o

Now the macro can be used in both the list of dependencies as well as on the f77 link command for target pattern in makefile:

pattern: $(OBJ) f77 $(OBJ) -lcore77 -lcore -lsunwindow \ -lpixrect -o pattern

For macro strings with single-letter names, the parentheses can be omitted.

You can use the Make Macros dialog box in Sun WorkShop to add macros to or delete macros from the Macros list in your WorkShop target and reassign values for makefile macros in the list. For more information, see Using Makefile Macros.

The initial values of makefile macros can be overridden with command-line options to make. For example, you have the following line at the top of makefile:

FFLAGS=-u

You also have the compile-line of computepts.f:

f77 $(FFLAGS) -c computepts.f

You have the final link:

f77 $(FFLAGS) $(OBJ) -lcore77 -lcore -lsunwindow \ lpixrect -o pattern

A make command without arguments uses the value of FFLAGS set above. However, this can be overridden from the command line:

% make "FFLAGS=-u -O"

The definition of the FFLAGS macro on the make command line overrides the makefile initialization, and both the -O flag and the -u flag are passed to f77. FFLAGS= can also be used on the command line to reset the macro so that it has no effect.