mpconstest Subtests

cons1 

Each CPU writes to successive locations with a stride size of byte, half word, or full word. This subtest creates contention for a single cache line. No other loads or stores are performed between successive writes to shared memory. 

cons2 

Each CPU reads from a location that is cachesize bytes away from the last written location. Every read causes the previously written line to be written back. The test runs until the CPU has accessed all lines in the cache.

cons3 

Similar to cons1 except that only one double word of each line is accessed. This creates simultaneous contention for multiple cache lines rather than a single line. 

cons4 

Similar to cons2, except that each CPU performs one store byte (storeb) and one load byte (loadb) operation between the detection of ID and the write of the next CPU ID. The target of the storeb and loadb is a unique byte in the line the CPU just read. This target is recognized as a different double word in the shared line cachesize bytes.

cons5 

Similar to cons3 except that each CPU performs one storeb and one loadb operation between the detection of ID and the write of the next CPU ID. The target of the storeb is one unique byte of the next double word in the line that the CPU just read from the CPU ID. The storeb data is unique to each CPU and changes each time the address of the target line changes.

cons6 

Similar to cons1 except that only one double word of each line is accessed. This creates simultaneous contention for multiple cache lines rather than a single line. 

cons7 

Similar to cons3 except that each CPU performs two storeb and one loadh operations between the detection of the CPU ID and the write of the next CPU ID. The targets of the storebs and loadh are two consecutive bytes of a double word in a shared line which is not a part of the shared memory buffer containing the IDs. The address of the target storeb and loadh instructions is held constant. The first storeb instruction gains ownership of the cache line, and the second stroreb is performed as a write hit. This occurs at the same time other CPUs are reading and writing the shared line containing the IDs.

cons8 

Similar to cons3 except that each CPU performs one storeb and one loadb operation between the detection of the CPU ID and the write of the next CPU ID. The target of the storeb and loadb is one unique byte of a double word of a private (unshared) line whose line number is identical to the line number containing the IDs. The storeb data is unique to each CPU and changes each time the address of the line containing the IDs changes.

cons9 

Similar to cons8 except that the target of the storeb and loadb is one unique byte of a double word of a private line whose address does not change through the entire test.

cons10 

Similar to cons9 except that two storeb and two loadb operations are performed to private (unshared) lines.The target of the second storeb is cachesize bytes away from the target of the first storeb. In a direct map cache, this results in a writeback of the unshared data written with the first storeb. The loadb operations are performed after the storeb in order to ensure that the writeback occurs correctly.

cons11 

Similar to cons10 except that the target of the storeb and loadb operations is to a shared line rather than a private line.

cons12 

Similar to cons7 except that two store double (stored) and load double (loadd) operations are used in place of the storeb and loadb operations. The target of the stored and loadd operations are two consecutive double words of a shared line. This test is designed to verify that the double word operations are performed correctly while the shared and owned state of the line containing the ID is changing.

cons13 through cons17 

These tests are similar variations of intermediate operations, stride size etc, and do not involve any new interfaces.