POST Output Reference

POST error messages use the following syntax:

c:s > ERROR: TEST = failing-test
c:s > H/W under test = FRU
c:s > Repair Instructions: Replace items in order listed by H/W 
under test above    
c:s > MSG = test-error-message
c:s > END_ERROR

In this syntax, c = the core number, s = the strand number.

Warning messages use the following syntax:

WARNING: message

Informational messages use the following syntax:

INFO: message

In the following example, POST reports an uncorrectable memory error affecting DIMM locations /SYS/MB/CMP0/BOB0/CH0/D0 and /SYS/MB/CMP0/BOB1/CH0/D0. The error was detected by POST.

2011-07-03 18:44:13.359 0:7:2>Decode of Disrupting Error Status Reg
(DESR HW Corrected)  bits 00300000.00000000
2011-07-03 18:44:13.517 0:7:2>        1    DESR_SOCSRE:     SOC
(non-local) sw_recoverable_error.
2011-07-03 18:44:13.638 0:7:2>        1    DESR_SOCHCCE:     SOC
(non-local) hw_corrected_and_cleared_error.
2011-07-03 18:44:13.773 0:7:2>
2011-07-03 18:44:13.836 0:7:2>Decode of NCU Error Status Reg bits
00000000.22000000
2011-07-03 18:44:13.958 0:7:2>        1    NESR_MCU1SRE:     MCU1 issued
a Software Recoverable Error Request
2011-07-03 18:44:14.095 0:7:2>        1    NESR_MCU1HCCE:     MCU1
issued a Hardware Corrected-and-Cleared Error Request
2011-07-03 18:44:14.248 0:7:2>
2011-07-03 18:44:14.296 0:7:2>Decode of Mem Error Status Reg Branch 1
bits 33044000.00000000
2011-07-03 18:44:14.427 0:7:2>        1      MEU 61     R/W1C Set to 1
on an UE if VEU = 1, or VEF = 1, or higher priority error in same cycle.
2011-07-03 18:44:14.614 0:7:2>        1      MEC 60     R/W1C Set to 1
on a CE if VEC = 1, or VEU = 1, or VEF = 1, or another error in same cycle.
2011-07-03 18:44:14.804 0:7:2>        1      VEU 57     R/W1C Set to 1 
on an UE, if VEF = 0 and no fatal error is detected in same cycle.
2011-07-03 18:44:14.983 0:7:2>        1      VEC 56     R/W1C Set to 1
on a CE, if VEF = VEU = 0 and no fatal or UE is detected in same cycle.
2011-07-03 18:44:15.169 0:7:2>        1      DAU 50     R/W1C Set to 1
if the error was a DRAM access UE.
2011-07-03 18:44:15.304 0:7:2>        1      DAC 46     R/W1C Set to 1
if the error was a DRAM access CE.
2011-07-03 18:44:15.440 0:7:2>
2011-07-03 18:44:15.486 0:7:2>        DRAM Error Address Reg for Branch
1 = 00000034.8647d2e0
2011-07-03 18:44:15.614 0:7:2>            Physical Address is
00000005.d21bc0c0
2011-07-03 18:44:15.715 0:7:2>        DRAM Error Location Reg for Branch
1 = 00000000.00000800
2011-07-03 18:44:15.842 0:7:2>        DRAM Error Syndrome Reg for Branch
1 = dd1676ac.8c18c045
2011-07-03 18:44:15.967 0:7:2>        DRAM Error Retry Reg for Branch 1
= 00000000.00000004
2011-07-03 18:44:16.086 0:7:2>        DRAM Error RetrySyndrome 1 Reg for
Branch 1 = a8a5f81e.f6411b5a
2011-07-03 18:44:16.218 0:7:2>        DRAM Error Retry Syndrome 2 Reg
for Branch 1 = a8a5f81e.f6411b5a
2011-07-03 18:44:16.351 0:7:2>        DRAM Failover Location 0 for
Branch 1 = 00000000.00000000
2011-07-03 18:44:16.475 0:7:2>        DRAM Failover Location 1 for
Branch 1 = 00000000.00000000
2011-07-03 18:44:16.604 0:7:2>
2011-07-03 18:44:16.648 0:7:2>ERROR: POST terminated prematurely. Not
all system components tested.
2011-07-03 18:44:16.786 0:7:2>POST: Return to VBSC
2011-07-03 18:44:16.795 0:7:2>ERROR:
2011-07-03 18:44:16.839 0:7:2>    POST toplevel status has the following
failures:
2011-07-03 18:44:16.952 0:7:2>    Node 0 -------------------------------
2011-07-03 18:44:17.051 0:7:2>        /SYS/MB/CMP0/BOB0/CH1/D0
2011-07-03 18:44:17.145 0:7:2>        /SYS/MB/CMP0/BOB1/CH1/D0
2011-07-03 18:44:17.241 0:7:2>END_ERROR

Related Information

• Oracle ILOM Properties That Affect POST Behavior

• Run POST With Maximum Testing

• Clear POST-Detected Faults