The uncore feature of the perf event subsystem implements Performance Monitoring Unit (PMU) support for the Intel Xeon Processor X55xx and X56xx processor families. Multiple processor cores can share physical uncore subsystems, including the L3 cache. Uncore PMU support allows packages to collect performance data, including load latency at various levels in the cache and memory hierarchy, which ranges from micro-operation dispatch up to globally observable data. Debugging in perf is made possible by the implementation of PMU event parsing.