BIOS POST Codes

B.1 Power-On Self-Test (POST)

The system BIOS provides a rudimentary power-on self-test. The basic devices required for the server to operate are checked, memory is tested, the LSI 1064 disk controller and attached disks are probed and enumerated, and the two Intel dual-gigabit Ethernet controllers are initialized.

The progress of the self-test is indicated by a series of POST codes.

These codes are displayed at the bottom right corner of the system’s VGA screen (once the self-test has progressed far enough to initialize the video monitor). However, the codes are displayed as the self-test runs and scroll off of the screen too quickly to be read. An alternate method of displaying the POST codes is to redirect the output of the console to a serial port (see Redirecting Console Output).

The message, BMC Responding is displayed at the end of POST.

B.1.1 How BIOS POST Memory Testing Works

The BIOS POST memory testing is performed as follows:

1. The first megabyte of DRAM is tested by the BIOS before the BIOS code is shadowed (that is, copied from ROM to DRAM).

2. Once executing out of DRAM, the BIOS performs a simple memory test (a write/read of every location with the pattern 55aa55aa).

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   Note - This memory test is performed only if Quick Boot is not enabled from the Boot Settings Configuration screen. Enabling Quick Boot causes the BIOS to skip the memory test. See Changing POST Options for more information.

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   Note - The memory test can take several minutes. You can escape from POST testing by pressing any key during POST.

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3. The BIOS polls the memory controllers for both correctable and uncorrectable memory errors and logs those errors into the service processor.