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SPARC Assembly Language Reference Manual
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Document Information

Preface

1.  SPARC Assembler for SunOS 5.x

2.  Assembler Syntax

3.  Executable and Linking Format

4.  Converting Files to the New Format

5.  Instruction-Set Mapping

A.  Pseudo-Operations

B.  Examples of Pseudo-Operations

C.  Using the Assembler Command Line

D.  An Example Language Program

E.  SPARC-V9 Instruction Set

E.1 SPARC-V9 Changes

E.1.1 Registers

E.1.2 Alternate Space Access

E.1.3 Byte Order

E.2 SPARC-V9 Instruction Set Changes

E.2.1 Extended Instruction Definitions to Support the 64-bit Model

E.2.2 Added Instructions to Support 64 bits

E.2.3 Added Instructions to Support High-Performance System Implementation

E.2.4 Deleted Instructions

E.2.5 Miscellaneous Instruction Changes

E.3 SPARC-V9 Instruction Set Mapping

E.4 SPARC-V9 Floating-Point Instruction Set Mapping

E.5 SPARC-V9 Synthetic Instruction-Set Mapping

E.6 UltraSPARC and VIS Instruction Set Extensions

E.6.1 Graphics Data Formats

E.6.2 Eight-bit Format

E.6.3 Fixed Data Formats

E.6.4 SHUTDOWN Instruction

E.6.5 Graphics Status Register (GSR)

E.6.6 Graphics Instructions

E.6.7 Memory Access Instructions

Index

E.5 SPARC-V9 Synthetic Instruction-Set Mapping

Here is a mapping of synthetic instructions to hardware equivalent instructions.

Table E-12

Synthetic Instruction
Hardware Equivalent(s)
Comment
cas

casl

casx

casxl

[regrsl], regrs2, regrd

[regrsl], regrs2, regrd

[regrsl], regrs2, regrd

[regrsl], regrs2, regrd

casa

casa

casxa

casxa

[regrsl]ASI_P, regrs2, regrd

[regrsl]ASI_P_L, regrs2, regrd

[regrsl]ASI_P, regrs2, regrd

[regrsl]ASI_P_L, regrs2, regrd

Compare & swap (cas)

cas little-endian

cas extended

cas little-endian, extended

clrx
[address]
stx
%g0, [address]
Clear extended word
clruw

clruw

regrs1, regrd

regrd

srl

srl

regrs1, %g0, regrd

regrd, %g0, regrd

Copy and clear upper word

Clear upper word

iprefetch
label
bn, pt
%xcc, label
Instruction prefetch,
mov

mov

mov

%y, regrd

%asrn, regrd

reg_or_imm, %asrn

rd

rd

wr

%y, regrd

%asrn, regrd

%g0, reg_or_imm, %asrn

ret

retl

jmpl

jmpl

%i7+8, %g0

%o7+8, %g0

Return from subroutine

Return from leaf subroutine

setn
value, r1, r2
for -xarch=v9 same as setx value r1, r2

for -xarch=v8 same as set value r2

setnhi
value, r1, r2
for -xarch=v9 same as setxhi value r1, r2

for -xarch=v8 same as sethi value r2

setuw
value,regrd
sethi

or

sethi

or

%hi(value), regrd

%g0, value, regrd

%hi(value), regrd;

regrd, %lo(value), regrd

(value & 3FF16)==0

when 0 ≤ value 4095

(otherwise)

Do not use setuw in a DCTI delay slot.

setsw
value,regrd
sethi

or

sethi

sra

sethi

or

sethi

or

sra

%hi(value), regrd

%g0, value, regrd

%hi(value), regrd

regrd, %g0, regrd

%hi(value), regrd;

regrd, %lo(value), regrd

%hi(value), regrd;

regrd, %lo(value), regrd

regrd, %g0, regrd

value>=0 and (value & 3FF16)==0

-4096 ≤ value ≤ 4095

if (value<0) and ((value & 3FF)==0)

(otherwise, if value>=0)

(otherwise, if value<0)

Do not use setsw in a CTI delay slot.

setx
value, r1, r2
sethi

or

sethi

or

sllx

or

%hh(value), r1

r1, %hm(value), r1

%lm(value), r2

r2, %lo(value), r2

r1, 32, r1

r1, r2, r2

setxhi
value r1, r2
sethi

or

sethi

sllx

or

%hh(value), r1

r1, %hm(value), r1

%lm(value), r2

r1, 32, r1

r1, r2, r2

signx

signx

regrsl, regrd

regrd

sra

sra

regrsl, %g0, regrd

regrd, %g0, regrd

Sign-extend 32-bit value to 64 bits