csx_AccessConfigurationRegister(9F)
csx_Parse_CISTPL_BYTEORDER(9F)
csx_Parse_CISTPL_CFTABLE_ENTRY(9F)
csx_Parse_CISTPL_DEVICEGEO(9F)
csx_Parse_CISTPL_DEVICEGEO_A(9F)
csx_Parse_CISTPL_DEVICE_OA(9F)
csx_Parse_CISTPL_DEVICE_OC(9F)
csx_Parse_CISTPL_LINKTARGET(9F)
csx_Parse_CISTPL_LONGLINK_A(9F)
csx_Parse_CISTPL_LONGLINK_C(9F)
csx_Parse_CISTPL_LONGLINK_MFC(9F)
ddi_get_soft_iblock_cookie(9F)
ddi_intr_get_supported_types(9F)
ddi_prop_lookup_byte_array(9F)
ddi_prop_lookup_int64_array(9F)
ddi_prop_lookup_string_array(9F)
ddi_prop_update_byte_array(9F)
ddi_prop_update_int64_array(9F)
ddi_prop_update_string_array(9F)
ldi_prop_lookup_byte_array(9F)
ldi_prop_lookup_int64_array(9F)
ldi_prop_lookup_string_array(9F)
mac_prop_info_set_default_link_flowctrl(9F)
mac_prop_info_set_default_str(9F)
mac_prop_info_set_default_uint8(9F)
mac_prop_info_set_range_uint32(9F)
net_event_notify_unregister(9F)
net_instance_notify_register(9F)
net_instance_notify_unregister(9F)
net_instance_protocol_unregister(9F)
net_protocol_notify_register(9F)
nvlist_lookup_boolean_array(9F)
nvlist_lookup_boolean_value(9F)
nvlist_lookup_nvlist_array(9F)
nvlist_lookup_string_array(9F)
nvlist_lookup_uint16_array(9F)
nvlist_lookup_uint32_array(9F)
nvlist_lookup_uint64_array(9F)
nvpair_value_boolean_array(9F)
scsi_get_device_type_scsi_options(9F)
usb_get_current_frame_number(9F)
usb_get_max_pkts_per_isoc_request(9F)
usb_pipe_get_max_bulk_transfer_size(9F)
usb_pipe_stop_intr_polling(9F)
usb_pipe_stop_isoc_polling(9F)
- Report Power Management capability of a PCI device
#include <sys/ddi.h> #include <sys/sunddi.h> int pci_report_pmcap(dev_info_t *dip, int cap, void *arg);
Solaris DDI specific (Solaris DDI)
Pointer to the device's dev_info structure
Power management capability
Argument for the capability
Some PCI devices provide power management capabilities in addition to those provided by the PCI Power Management Specification. The pci_report_pmcap(9F) function reports those Power Management capabilities of the PCI device to the framework. Framework supports dynamic changing of the capability by allowing pci_report_pmcap(9F) to be called multiple times. Following are the supported capabilities as indicated by the cap:
PCI_PM_IDLESPEED — The PCI_PM_IDLESPEED value indicates the lowest PCI clock speed that a device can tolerate when idle, and is applicable only to 33 MHz PCI bus. arg represents the lowest possible idle speed in KHz (1 KHz is 1000 Hz). The integer value representing the speed should be cast to (void *) before passing as arg to pci_report_pmcap(9F).
The special values of arg are:
The device can tolerate any idle clock speed.
The device cannot tolerate slowing down of PCI clock even when idle.
If the driver doesn't make this call, PCI_PM_IDLESPEED_NONE is assumed. In this case, one offending device can keep the entire bus from being power managed.
The pci_report_pmcap(9F) function returns:
Successful reporting of the capability
Failure to report capability because of invalid argument(s)
The pci_report_pmcap(9F) function can be called from user, kernel and interrupt context.
1. A device driver knows that the device it controls works with any clock between DC and 33 MHz as specified in Section 4.2.3.1: Clock Specification of the PCI Bus Specification Revision 2.1. The device driver makes the following call from its attach(9E):
if (pci_report_pmcap(dip, PCI_PM_IDLESPEED, PCI_PM_IDLESPEED_ANY) != DDI_SUCCESS) cmn_err(CE_WARN, "%s%d: pci_report_pmcap failed\n", ddi_driver_name(dip), ddi_get_instance(dip));
2. A device driver controls a 10/100 Mb Ethernet device which runs the device state machine on the chip from the PCI clock. For the device state machine to receive packets at 100 Mb, the PCI clock cannot drop below 4 MHz. The driver makes the following call whenever it negotiates a 100 Mb Ethernet connection:
if (pci_report_pmcap(dip, PCI_PM_IDLESPEED, (void *)4000) != DDI_SUCCESS) cmn_err(CE_WARN, "%s%d: pci_report_pmcap failed\n", ddi_driver_name(dip), ddi_get_instance(dip));
See attributes(5) for descriptions of the following attributes:
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Writing Device Drivers
PCI Bus Power Management Interface Specification Version 1.1
PCI Bus Specification Revision 2.1