C.1.8.2 Parallel Port

The parallel port is supported by an IEEE 1284-compatible parallel port controller that is located on the SuperIO component. The parallel port controller is a PC-industry-standard controller that achieves a 2-megabits per second (Mbps) data transfer rate. The parallel port controller interface supports the ECP protocol as well as the following:

• Centronics - Provides a widely accepted parallel port interface.

• Compatibility - Provides an asynchronous, byte-wide forward (host to peripheral) channel with data and status lines used according to their original definitions.

• Nibble mode - Provides an asynchronous, reverse (peripheral-to-host) channel, under control of the host. Data bytes are transmitted as two sequential, 4-bit nibbles using four peripheral-to-host status lines.

Parallel Port Cables

The parallel port cable is IEEE1284 compliant and comprises 18 pairs of signal wires that are double shielded with braid and foil. The maximum length of the parallel port cable is 2.2 yards (2 meters).

Electrical Characteristics

Drivers operate at a nominal 5-VDC transistor-transistor logic (TTL) levels. The maximum open circuit voltage is 5.5 VDC and the minimum is -0.5 VDC. A logic high-level signal is at least 2.4 VDC at a source current of 0.32 mA and a logic low-level signal is no more than 0.4 VDC at a sink current of 14 mA.

Receivers also operate at nominal 5-VDC TTL levels and can withstand peak voltage transients between -2 VDC and 7 VDC without damage or improper operation. The high-level threshold is less than or equal to 2.0 VDC and the low-level threshold is at least 0.8 VDC. Sink current is less than or equal to 0.32 mA at 2.0 VDC and source current is less than or equal to 12 mA at 0.8 VDC.