C.1.12.5 FBC

The frame buffer controller (FBC) ASIC is the graphics draw ASIC that provides interface between the UPA and the 3DRAM. The FBC ASIC provides 2D and 3D graphics draw acceleration. Highlights of the FBC ASIC features include:

• UPA slave device with write-mostly philosophy

• Interfaces with 3DRAM to achieve accelerated graphics performance

• Supports single buffered and DBZ configurations

• Supports frame buffer-to-frame buffer copy

• Supports viewport clipping, picking, and pixel processing

• Supports byte, plane masks, raster operations, blend operations, and conditional writes in 3DRAM

• 83.3-MHz UPA operation and 75-MHz 3DRAM operation

• 3.3-VDC and 5-VDC (for RAMDAC ASIC) supply voltage