PCI Basic Cycles

The following are definitions of the PCI basic transaction cycle for each bus.

Address Phase--Every PCI transaction begins with this phase, which includes concurrent hidden arbitration.

The initiator identifies the target device and transaction type.

Data Phase--At the end of the address phase, the address/data bus transfers data in one or more data phases. The clock immediately following the Address Phase begins the data phase.

During the data phase, a data object is transferred between initiator and target during every rising edge of the PCI bus clock.

Bus Idle State - When the last data transfer has finished, the initiator returns the bus to the idle state, which is the condition of having no transaction in progress on the bus.