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x86 Assembly Language Reference Manual     Oracle Solaris 11 Express 11/10
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Document Information

Preface

1.  Overview of the Solaris x86 Assembler

2.  Solaris x86 Assembly Language Syntax

3.  Instruction Set Mapping

Instruction Overview

General-Purpose Instructions

Data Transfer Instructions

Binary Arithmetic Instructions

Decimal Arithmetic Instructions

Logical Instructions

Shift and Rotate Instructions

Bit and Byte Instructions

Control Transfer Instructions

String Instructions

I/O Instructions

Flag Control (EFLAG) Instructions

Segment Register Instructions

Miscellaneous Instructions

Floating-Point Instructions

Data Transfer Instructions (Floating Point)

Basic Arithmetic Instructions (Floating-Point)

Comparison Instructions (Floating-Point)

Transcendental Instructions (Floating-Point)

Load Constants (Floating-Point) Instructions

Control Instructions (Floating-Point)

SIMD State Management Instructions

MMX Instructions

Data Transfer Instructions (MMX)

Conversion Instructions (MMX)

Packed Arithmetic Instructions (MMX)

Comparison Instructions (MMX)

Logical Instructions (MMX)

Shift and Rotate Instructions (MMX)

State Management Instructions (MMX)

SSE Instructions

SIMD Single-Precision Floating-Point Instructions (SSE)

Data Transfer Instructions (SSE)

Packed Arithmetic Instructions (SSE)

Comparison Instructions (SSE)

Logical Instructions (SSE)

Shuffle and Unpack Instructions (SSE)

Conversion Instructions (SSE)

MXCSR State Management Instructions (SSE)

64-Bit SIMD Integer Instructions (SSE)

Miscellaneous Instructions (SSE)

SSE2 Instructions

SSE2 Packed and Scalar Double-Precision Floating-Point Instructions

SSE2 Data Movement Instructions

SSE2 Packed Arithmetic Instructions

SSE2 Logical Instructions

SSE2 Compare Instructions

SSE2 Shuffle and Unpack Instructions

SSE2 Conversion Instructions

SSE2 Packed Single-Precision Floating-Point Instructions

SSE2 128-Bit SIMD Integer Instructions

SSE2 Miscellaneous Instructions

Operating System Support Instructions

64-Bit AMD Opteron Considerations

Index

MMX Instructions

The MMX instructions enable x86 processors to perform single-instruction, multiple-data(SIMD) operations on packed byte, word, doubleword, or quadword integer operands contained in memory, in MMX registers, or in general-purpose registers.

Data Transfer Instructions (MMX)

The data transfer instructions move doubleword and quadword operands between MMX registers and between MMX registers and memory.

Table 3-20 Data Transfer Instructions (MMX)

Solaris Mnemonic
Intel/AMD Mnemonic
Description
Notes
movd
MOVD
move doubleword
movdq valid only under -xarch=amd64
movq
MOVQ
move quadword
valid only under -xarch=amd64

Conversion Instructions (MMX)

The conversion instructions pack and unpack bytes, words, and doublewords.

Table 3-21 Conversion Instructions (MMX)

Solaris Mnemonic
Intel/AMD Mnemonic
Description
Notes
packssdw
PACKSSDW
pack doublewords into words with signed saturation
packsswb
PACKSSWB
pack words into bytes with signed saturation
packuswb
PACKUSWB
pack words into bytes with unsigned saturation
punpckhbw
PUNPCKHBW
unpack high-order bytes
punpckhdq
PUNPCKHDQ
unpack high-order doublewords
punpckhwd
PUNPCKHWD
unpack high-order words
punpcklbw
PUNPCKLBW
unpack low-order bytes
punpckldq
PUNPCKLDQ
unpack low-order doublewords
punpcklwd
PUNPCKLWD
unpack low-order words

Packed Arithmetic Instructions (MMX)

The packed arithmetic instructions perform packed integer arithmetic on packed byte, word, and doubleword integers.

Table 3-22 Packed Arithmetic Instructions (MMX)

Solaris Mnemonic
Intel/AMD Mnemonic
Description
Notes
paddb
PADDB
add packed byte integers
paddd
PADDD
add packed doubleword integers
paddsb
PADDSB
add packed signed byte integers with signed saturation
paddsw
PADDSW
add packed signed word integers with signed saturation
paddusb
PADDUSB
add packed unsigned byte integers with unsigned saturation
paddusw
PADDUSW
add packed unsigned word integers with unsigned saturation
paddw
PADDW
add packed word integers
pmaddwd
PMADDWD
multiply and add packed word integers
pmulhw
PMULHW
multiply packed signed word integers and store high result
pmullw
PMULLW
multiply packed signed word integers and store low result
psubb
PSUBB
subtract packed byte integers
psubd
PSUBD
subtract packed doubleword integers
psubsb
PSUBSB
subtract packed signed byte integers with signed saturation
psubsw
PSUBSW
subtract packed signed word integers with signed saturation
psubusb
PSUBUSB
subtract packed unsigned byte integers with unsigned saturation
psubusw
PSUBUSW
subtract packed unsigned word integers with unsigned saturation
psubw
PSUBW
subtract packed word integers

Comparison Instructions (MMX)

The compare instructions compare packed bytes, words, or doublewords.

Table 3-23 Comparison Instructions (MMX)

Solaris Mnemonic
Intel/AMD Mnemonic
Description
Notes
pcmpeqb
PCMPEQB
compare packed bytes for equal
pcmpeqd
PCMPEQD
compare packed doublewords for equal
pcmpeqw
PCMPEQW
compare packed words for equal
pcmpgtb
PCMPGTB
compare packed signed byte integers for greater than
pcmpgtd
PCMPGTD
compare packed signed doubleword integers for greater than
pcmpgtw
PCMPGTW
compare packed signed word integers for greater than

Logical Instructions (MMX)

The logical instructions perform logical operations on quadword operands.

Table 3-24 Logical Instructions (MMX)

Solaris Mnemonic
Intel/AMD Mnemonic
Description
Notes
pand
PAND
bitwise logical AND
pandn
PANDN
bitwise logical AND NOT
por
POR
bitwise logical OR
pxor
PXOR
bitwise logical XOR

Shift and Rotate Instructions (MMX)

The shift and rotate instructions operate on packed bytes, words, doublewords, or quadwords in 64–bit operands.

Table 3-25 Shift and Rotate Instructions (MMX)

Solaris Mnemonic
Intel/AMD Mnemonic
Description
Notes
pslld
PSLLD
shift packed doublewords left logical
psllq
PSLLQ
shift packed quadword left logical
psllw
PSLLW
shift packed words left logical
psrad
PSRAD
shift packed doublewords right arithmetic
psraw
PSRAW
shift packed words right arithmetic
psrld
PSRLD
shift packed doublewords right logical
psrlq
PSRLQ
shift packed quadword right logical
psrlw
PSRLW
shift packed words right logical

State Management Instructions (MMX)

The emms (EMMS) instruction clears the MMX state from the MMX registers.

Table 3-26 State Management Instructions (MMX)

Solaris Mnemonic
Intel/AMD Mnemonic
Description
Notes
emms
EMMS
empty MMX state