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x86 Assembly Language Reference Manual     Oracle Solaris 11 Express 11/10
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Document Information

Preface

1.  Overview of the Solaris x86 Assembler

2.  Solaris x86 Assembly Language Syntax

3.  Instruction Set Mapping

Instruction Overview

General-Purpose Instructions

Data Transfer Instructions

Binary Arithmetic Instructions

Decimal Arithmetic Instructions

Logical Instructions

Shift and Rotate Instructions

Bit and Byte Instructions

Control Transfer Instructions

String Instructions

I/O Instructions

Flag Control (EFLAG) Instructions

Segment Register Instructions

Miscellaneous Instructions

Floating-Point Instructions

Data Transfer Instructions (Floating Point)

Basic Arithmetic Instructions (Floating-Point)

Comparison Instructions (Floating-Point)

Transcendental Instructions (Floating-Point)

Load Constants (Floating-Point) Instructions

Control Instructions (Floating-Point)

SIMD State Management Instructions

MMX Instructions

Data Transfer Instructions (MMX)

Conversion Instructions (MMX)

Packed Arithmetic Instructions (MMX)

Comparison Instructions (MMX)

Logical Instructions (MMX)

Shift and Rotate Instructions (MMX)

State Management Instructions (MMX)

SSE Instructions

SIMD Single-Precision Floating-Point Instructions (SSE)

Data Transfer Instructions (SSE)

Packed Arithmetic Instructions (SSE)

Comparison Instructions (SSE)

Logical Instructions (SSE)

Shuffle and Unpack Instructions (SSE)

Conversion Instructions (SSE)

MXCSR State Management Instructions (SSE)

64-Bit SIMD Integer Instructions (SSE)

Miscellaneous Instructions (SSE)

SSE2 Instructions

SSE2 Packed and Scalar Double-Precision Floating-Point Instructions

SSE2 Data Movement Instructions

SSE2 Packed Arithmetic Instructions

SSE2 Logical Instructions

SSE2 Compare Instructions

SSE2 Shuffle and Unpack Instructions

SSE2 Conversion Instructions

SSE2 Packed Single-Precision Floating-Point Instructions

SSE2 128-Bit SIMD Integer Instructions

SSE2 Miscellaneous Instructions

Operating System Support Instructions

64-Bit AMD Opteron Considerations

Index

64–Bit AMD Opteron Considerations

To assemble code for the AMD Opteron CPU, invoke the assembler with the -xarch=amd64 command line option. See the as(1) man page for additional information.

The following Solaris mnemonics are only valid when the -xarch=amd64 command line option is specified:

adcq
cmovnoq
mulq
addq
cmovnpq
negq
andq
cmovnsq
notq
bsfq
cmovnzq
orq
bsrq
cmovoq
popfq
bswapq
cmovpeq
popq
btcq
cmovpoq
pushfq
btq
cmovpq
pushq
btrq
cmovsq
rclq
btsq
cmovzq
rcrq
cltq
cmpq
rolq
cmovaeq
cmpsq
rorq
cmovaq
cmpxchgq
salq
cmovbeq
cqtd
sarq
cmovbq
cqto
sbbq
cmovcq
decq
scasq
cmoveq
divq
shldq
cmovgeq
idivq
shlq
cmovgq
imulq
shrdq
cmovleq
incq
shrq
cmovlq
larq
sldtq
cmovnaeq
leaq
smswq
cmovnaq
lodsq
stosq
cmovnbeq
lslq
strq
cmovnbq
movabs
subq
cmovncq
movdq
testq
cmovneq
movntiq
xaddq
cmovngeq
movq
xchgq
cmovngq
movsq
xchgqA
cmovnleq
movswq
xorq
cmovnlq
movzwq

The following Solaris mnemonics are not valid when the -xarch=amd64 command line option is specified:

aaa
daa
lesw
aad
das
popa
aam
into
popaw
aas
jecxz
pusha
boundw
ldsw
pushaw