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System Overview page B-1 --------------------------------
System Architecture page B-2
System Board page B-2
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This chapter describes the SPARCstation 10 system architecture for all configurations:
See Chapter 1, "Product Description" for figures of the back panel.
The SPARCstation 10 system contains a system board, a power supply, up to two hard disk drives, a diskette drive. A variety of SBus cards and MBus modules can be installed on the system board.
Memory is installed using Dynamic Single Inline Memory Modules (DSIMMs). Up to eight DSIMMs can be installed. The S10BSX is additionally configured with one Video SIMM (VSIMM). The VSIMM uses the 13W3 connector built into the back panel for output. Up to two Video SIMMs can be installed in the S10BSX. When installing a second VSIMM in the system, an auxiliary video board with a 13W3 connector on the back of the board must also be installed into the auxiliary video board slot on the S10BSX.
All configurations of the SPARCstation 10 system implement the following:
On the system board are the following:
Figure B-1 shows a block diagram of the S10 service code system board. Figure B-2 shows a block diagram of the S10BSX service code system board.
Figure B-1 S10 System Board Block Diagram
Figure B-2 S10BSX System Board Block Diagram
Each system board supports one to four SBus cards. A wide variety of I/O options can be used with SBus cards, such as graphic displays, Ethernet, printers, and serial/parallel controllers.
The SPARC MBus is a high speed interface between the processor modules, physical memory, and I/O devices. The MBus is developed to operate at clock rates starting at 40 MHz, but can run at lower speeds such as 33 MHz and 36 MHz. The MBus interface has these features:
The MBus to SBus interface contains:
The MBus to SBus interface is contained in the MSBI chip on the S10BSX service code model and the MSI chip on the S10 service code model.
The IOMMU is used to perform address translations when SBus masters request the SBus.
Table B-1 lists the total amount of memory each system board can accommodate.
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System Board Total Memory Available (Mbytes) --------------------------------------------------------------------------------------
S10 512
S10BSX (with one VSIMM) 448*
S10BSX (with two VSIMMs) 384*
* One SIMM slot is allocated for a VSIMM (configured at the
factory).
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The SPARCstation 10 memory system has a 128-bit wide data path with 16-bits of error correcting code (ECC). The memory system implementation with the Error Correcting Code Memory Controller (EMC) or Scalable Memory Controller (SMC) uses 80-nanosecond DSIMMs to achieve 100-nanosecond data access time. The EMC is an S10 service code model component. The SMC is an S10BSX service code model component.
Table B-2 lists the densities of DRAMs on DSIMMs supported by the Error Correcting Code Memory Controller (EMC) or Scalable Memory Controller (SMCs:
Table B-2 Densities of DRAMs on DSIMMs Supported
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RAM Density Number of RAMs Capacity Type --------------------------------------------------
4 Mbit 1Mx4 36 16 Mbyte ECC DRAM
16 Mbit 4Mx4 36 64 Mbyte ECC DRAM
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Figure B-3 illustrates the DSIMM memory system.
Figure B-3 DSIMM Memory System
Note - Only the S10BSX service code model supports Video SIMMs.
Video SIMMs (VSIMMs) contain a video buffer chip (VBC) that handles video refresh, and a memory display interface chip (MDI) that muxes data from the VRAM to the DAC. The MDI contains look up tables and blend logic. There is also a DAC on the video SIMMs and pixel clock generation circuitry.
The densities of VRAMs on VSIMMs supported by the Scalable Memory Controller (SMC) are listed in Table B-3:
Table B-3 Densities of VRAMs on VSIMMs Supported
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RAM Density Number of RAMs Capacity Type per VSIMM --------------------------------------------------------
1 Mbit 256Kx4 32 4 Mbyte 128 bit VRAM
2 Mbit 256Kx8 32 8 Mbyte 256 bit VRAM
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The S10BSX service code model with the Scalable Memory Controller (SMC) uses 80-nanosecond VRAMs to provide for 100-nanosecond data access timing.
Presently, two versions of the VSIMMs are available for the S10BSX service code model:
Figure B-4 illustrates the VSIMM memory system.
Figure B-4 VSIMM Memory System Diagram
The Memory Display Interface chip (MDI) muxes data from the VRAMs to the DAC. The MDI contains:
The MDI can process 8-bit greyscale, 8-bit pseudo-color, and 16-bit and 32-bit pixels. Using a 4 Mbyte VSIMM, it can support 1152x900 pixel displays running at 76 MHz in full 32-bit true color mode. Using an 8 Mbyte VSIMM, it provides support for 1280x1024 and 1600x1280 monitors at 76 MHz. It can also support 84 MHz monitors with 1152x900 resolution.
There is a Video Buffer Chip (VBC) on each VSIMM. It performs VRAM reload and refresh operations for that VSIMM which allows multiple independent VSIMMs with respective monitors.
Two ASICs can function as memory controllers - either the Error Correcting Code Memory Controller (EMC) or the Scalable Memory Controller (SMC). The SMC and EMC ASICs are pin compatible. Either one or the other is used.
In the S10BSX service code, the SMC (Scalable Memory Controller) contains SPAM (Sun Pixel Arithmetic Memory) and EMC (Error Correcting Code Memory Controller chip. The EMC portion interfaces both the system main memory (DSIMMs) and video memory (VSIMMs) to the MBus.
Table B-4 illustrates the system type each ASIC is used in and the function of the ASIC.
Table B-4 Description of Memory Controllers
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ASIC Service Code Service Code Function S10 S10BSX ---------------------------------------------------------
EMC 3 Simple memory controller
No graphics and imaging
controller
SMC 3 Superset of the EMC
Contains a graphics and
imaging controller
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The SBus to SCSI, Ethernet, and Parallel Interface (MACIO) ASIC is the interface between the SBus and the following devices:
on systems with S10BSX service code. This ASIC integrates three chips:
Figure B-5 illustrates a chip-level functional block diagram of the SBus to SCSI, Ethernet, and parallel interface on the S10BSX service code.
Figure B-5 SBus to SCSI and Ethernet and Parallel Interface (MACIO) Chip-Level Functional Block Diagram
The SBus to External SBus Interface ASIC is the interface between the SBus and the external bus on systems with the S10 and S10BSX service codes. The external bus connects two serial port chips, an audio chip, the diskette drive controller, the 4-Mbit EEPROM, the TOD/NVRAM chip, and the interface to the LED. One of the serial port chips provides serial ports A and B. The other serial port chip provides the keyboard and mouse port. Line drivers interface the two serial port chips to the serial ports.
Figure B-6 provides a diagram of the SEC chip.
Figure B-6 SEC Chip Diagram
The clock chip provides the MBus and SBus clocks for the system board and the VSIMMs. There are fourteen MBus clocks generated by the clock chip, one for each receiver.
There are also six SBus clocks:
Table B-5 lists the SPARCstation 10 power requirements.
Table B-5 Power Supply Requirements
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VDC Current Peak Current (Amps) (Amps) ----------------------------
5 20.5 20.5
+12 3.0 5.0
-12 0.1 0.1
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