A P P E N D I X  B

BIOS POST Codes

This appendix lists the BIOS POST code checkpoints for the Sun Blade X6240 server module.


B.1 POST Code Checkpoints

The POST code checkpoints are the largest set of checkpoints during the BIOS preboot process. TABLE B-1 describes the checkpoints that might occur during the POST portion of the BIOS. These two-digit checkpoints are the output from primary I/O port 80.


TABLE B-1 POST Code Checkpoints

Post Code

Description

03

Disable NMI, Parity, video for EGA, and DMA controllers. Initialize BIOS, POST, Runtime data area. Also initialize BIOS modules on POST entry and GPNV area. Initialize CMOS as mentioned in the Kernel Variable “wCMOSFlags.”

04

Check the CMOS diagnostic byte to determine if battery power is OK and the CMOS checksum is OK. Verify that CMOS checksum manually by reading storage area. If the CMOS checksum is bad, update CMOS with power-on default values and clear passwords. Initialize status register A. Initializes data variables that are based on CMOS setup questions. Initializes both the 8259 compatible PICs in the system.

05

Initializes the interrupt controlling hardware (generally PIC) and interrupt vector table.

06

Do R/W test to CH-2 count reg. Initialize CH-0 as system timer. Install the POSTINT1Ch handler. Enable IRQ-0 in PIC for system timer interrupt. Traps INT1Ch vector to POSTINT1ChHandlerBlock.

07

Fixes CPU POST interface calling pointer.

08

Initializes the CPU. The BAT test is being done on KBC. Program the keyboard controller command byte is being doen after Auto detection of KB/MS using AMI KB-5.

C0

Early CPU Init Start--Disable Cache--Init Local APIC.

C1

Set up boot strap processor information.

C2

Set up boot strap processor for POST.

C5

Enumerate and set up application processors.

C6

Re-enables cache for boot strap processor.

C7

Early CPU Init Exit.

0A

Initializes the 8042 compatible Keyboard Controller.

0B

Detects the presence of PS/2 mouse.

0C

Detects the presence of Keyboard in KBC port.

0E

Testing and initialization of different input devices. Also, update the kernel variables. Traps the INT09h vector, so that the POST INT09h handler gets control for IRQ1. Decompress all available language, BIOS logo, and Silent logo modules.

13

Early POST initialization of chipset registers.

20

Relocate System Management Interrupt vector for all CPUs in the system.

24

Decompresses and initializes any platform-specific BIOS modules. GNPV is initialized at this checkpoint.

2A

Initializes different devices through DIM.

2C

Initializes different devices. Detects and initializes the video adapter installed in the system that have optional ROMs.

2E

Initializes all the output devices.

31

Allocates memory for ADM module and decompresses it. Gives control to ADM module for initialization. Initializes language and font modules for ADM. Activates ADM module.

33

Initializes the silent boot module. Sets the window for displaying text information.

37

Displays sign-on message, CPU information, setup key message, and any OEM-specific information.

38

Initializes different devices through DIM. USB controllers are initialized at this point.

39

Initializes DMAC-1 and DMAC-2.

3A

Initializes RTC date/time.

3B

Test for total memory installed in the system. Also, check for DEL or ESC keys to limit memory test. Display total memory in the system.

3C

Mid POST initialization of chipset registers.

40

Detect different devices (parallel ports, serial ports, and coprocessor in CPU, etc.) successfully installed in the system and update the BDA, EBDA, etc.

52

Updates CMOS memory size from memory found in memory test. Allocates memory for Extended BIOS Data Area from base memory. Programming the memory hole or any kind of implementation that needs an adjustment in system RAM size if needed.

60

Initializes NUM-LOCK status and programs the KBD typematic rate.

75

Initialize Int-13 and prepare for IPL detection.

78

Initializes IPL devices controlled by BIOS and option ROMs.

7C

Generate and write contents of ESCD in NVRam.

84

Log errors encountered during POST.

85

Display errors to the user and gets the user’s response to the error.

87

Execute BIOS setup if needed/requested. Check boot password if installed.

8C

Late POST initialization of chipset registers.

8D

Build ACPI tables (if ACPI is supported).

8E

Program the peripheral parameters. Enable/Disable NMI as selected.

90

Initialization of system management interrupt by invoking all handlers.

A1

Clean-up work needed before booting to OS.

A2

Takes care of runtime image preparation for different BIOS modules. Fill the free area in F000h segment with 0FFh. Initializes the Microsoft IRQ Routing Table. Prepares the runtime language module. Disables the system configuration display if needed.

A4

Initialize runtime language module. Display boot option popup menu.

A7

Displays the system configuration screen if enabled. Initializes the CPUs before boot, which includes the programming of the MTRRs.

A9

Wait for user input at config display if needed.

AA

Uninstall POST INT1Ch vector and INT09h vector.

AB

Prepare BBS for Int 19 boot. Initialize MP tables.

AC

End of POST initialization of chipset registers. De-initializes the ADM module.

B1

Save system context for ACPI. Prepare CPU for OS boot including final MTRR values.

00

Prepares CPU for booting to OS by copying all of the context of the BSP to all application processors present. NOTE: APs are left in the CLIHLT state.

61h-70h

OEM POST error. This range is reserved for chipset vendors and system manufacturers. The error associated with this value may be different from one platform to the next.