C.1.3 UltraSPARC II Processor

The UltraSPARC II processor is a high-performance, highly-integrated superscalar processor implementing the SPARC-V9 64-bit RISC architecture. The UltraSPARC II processor is capable of sustaining the execution of up to four instructions per cycle even in the presence of conditional branches and cache misses. This sustained performance is supported by a decoupled prefetch and dispatch unit with instruction buffer.

The UltraSPARC II processor supports both 2D and 3D graphics, as well as image processing, video compression and decompression, and video effects through the sophisticated visual instruction set (VIS). VIS provides high levels of multimedia performance, including real-time video compression/decompression and two streams of MPEG-2 decompression at full broadcast quality with no additional hardware support. The UltraSPARC II processor provides a 2-Mbyte ecache, with an 300-MHz operating frequency.

UltraSPARC II processor characteristics and associated features include:

• SPARC-V9 architecture compliant

• Binary compatible with all SPARC application code

• Multimedia capable visual instruction set (VIS)

• Multiprocessing support

• Glueless four-processor connection with minimum latency

• Snooping cache coherency

• Four-way superscalar design with nine execution units; four integer execution units

• Three floating-point execution units

• Two graphics execution units

• Selectable little- or big-endian byte ordering

• 64-bit address pointers

• 16-Kbyte non-blocking data cache

• 16-Kbyte instruction cache; single cycle branch following

• Power management

• Software prefetch instruction support

• Multiple outstanding requests