C.1.10.6 MII Port Timing

MII port timing encompasses two configurations involving the use of either an on-board transceiver or external transceivers. For either transceiver configuration, the MII port timing is the same because MII operates with a 40-nanosecond cycle time.

MII is used to interconnect both integrated circuits and circuit assemblies. This enables separate signal transmission paths to exist between the reconciliation sublayer, embedded in the PCIO ASIC, and a local PHY IC, and between the reconciliation sublayer and a remote PHY IC. The unidirectional paths between the reconciliation sublayer and the local PHY IC are composed of sections A1, B1, C1 and D1. The unidirectional paths between the reconciliation sublayer and the remote PHY IC are composed of sections A2, B2, C2, and D2.