When the server is started or rebooted, the BIOS POST tests memory by performing a write/read test of every location using the pattern 55aa. Then BIOS polls the memory controllers for both correctable and non correctable memory errors, and logs those errors into the SP SEL.
BIOS does not perform this test if Quick Boot is enabled.
For more information about BIOS POST, see BIOS POST.
See the following example:
Event# | Date | Time | Memory | Uncorrectable Error |Asserted | OEM Data-2 0x12 OEM Data-3 0x9d
Data-2 contains two nibbles (0x12 is “hex one and hex two” not “hex twelve”)
Consider the data from the preceding sample (0x12). In binary, it is 0001,0010.
Bits 6-7 = 00. This identifies the error as an ECC memory error. It should not change.
Bits 4-5 = 01. This identifies the memory branch. This number is unused in this context.
Bits 0-3 = 0010. Converted to decimal, these identify CPU node 2.
Nodes map to CPUs as follows:
The following table shows the mapping of nodes to CMODs and CPUs. In the physical system, CMOD 0 is on the bottom, and CMOD 3 is on the top.
In this example, the value 2 identifies CMOD 3, CPU 0.
Data–3 contains two nibbles (0x9d is “hex nine and hex d” not “hex nine d”). These numbers identify the DIMMs in the pair.
Consider the data from the preceding sample (0x9d). Converted to decimal it identifies DIMMs 9 and 13.