–xarch=isa - Oracle® Solaris Studio 12.4: Fortran User's Guide

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3.4.109 `–xarch=isa`

Specify instruction set architecture (ISA ).

The following table lists the -xarch keywords common to both SPARC and x86 platforms.

Table 3-13 -xarch keywords common to both SPARC and x86 platforms

Flag	Meaning
`generic`	Uses the instruction set common to most processors. This is the default.
`generic64`	Compile for good performance on most 64-bit platforms.This option is equivalent to `–m64` `–xarch=generic` and is provided for compatibility with earlier releases.
`native`	Compile for good performance on this system. The compiler chooses the appropriate setting for the current system processor it is running on.
`native64`	Compile for good performance on 64–bit this system. This option is equivalent to `–m64` `–xarch=native` and is provided for compatibility with earlier releases.

Note that although -xarch can be used alone, it is part of the expansion of the –xtarget option and may be used to override the-xarch value that is set by a specific -xtarget option. For example:

% f95 -xtarget=ultra2 -xarch=sparcfmaf ...

overrides the -xarch set by -xtarget=ultra2

This option limits the code generated by the compiler to the instructions of the specified instruction set architecture by allowing only the specified set of instructions. This option does not guarantee use of any target–specific instructions.

If this option is used with optimization, the appropriate choice can provide good performance of the executable on the specified architecture. An inappropriate choice results in a binary program that is not executable on the intended target platform.

Note the following:

Object binary files (.o) compiled with generic,sparc, sparcvis2, sparcvis3, sparcfmaf, sparcima can be linked and can execute together, but can only run on a processor supporting all the instruction sets linked.
For any particular choice, the generated executable might not run or run much more slowly on legacy architectures. Also, because quad-precision (REAL*16 and long double) floating-point instructions are not implemented in any of these instruction set architectures, the compiler does not use these instructions in the code it generates.

The default when -xarch is not specified is generic.

Table 3–14 gives details for each of the -xarch keywords on SPARC platforms.

Table 3-14 -xarch Values for SPARC Platforms

`-xarch=`	Meaning (SPARC)
`sparc`	Compile for the SPARC–V9 ISA. Compile for the V9 ISA, but without the Visual Instruction Set (VIS), and without other implementation-specific ISA extensions. This option enables the compiler to generate code for good performance on the V9 ISA.
`sparc4`	Compile for the SPARC4 version of the SPARC- V9 ISA. Enables the compiler to use instructions from the SPARC-V9 instruction set, plus the UltraSPARC extensions, which includes VIS 1.0, the UltraSPARC-III extensions, which includes VIS2.0, the fused floating-point multiply-add instructions, VIS 3.0, and SPARC4 instructions.
`sparc4b`	Compile for the SPARC4B version of the SPARC-V9 ISA. Enables the compiler to use instructions from the SPARC-V9 instruction set, plus the UltraSPARC extensions, which includes VIS 1.0, the UltraSPARC-III extensions, which includes VIS2.0, the SPARC64 VI extensions for floating-point multiply-add, the SPARC64 VII extensions for integer multiply-add, and the PAUSE and CBCOND instructions from the SPARC T4 extensions.
`sparc4c`	Compile for the SPARC4C version of the SPARC-V9 ISA. Enables the compiler to use instructions from the SPARC-V9 instruction set, plus the UltraSPARC extensions, which includes VIS 1.0, the UltraSPARC-III extensions, which includes VIS2.0, the SPARC64 VI extensions for floating-point multiply-add, the SPARC64 VII extensions for integer multiply-add, the VIS3B subset of the VIS 3.0 instructions a subset of the SPARC T3 extensions, called the VIS3B subset of VIS 3.0, and the PAUSE and CBCOND instructions from the SPARC T4 extensions.
`sparc5`	Compile for the SPARC5 version of the SPARC-V9 ISA. Enables the compiler to use instructions from the SPARC-V9 instruction set, plus the extensions, which includes VIS 1.0, the Ultra SPARC-III extensions, which includes VIS2.0, the fused floating-point multiply-add instructions, VIS 3.0, SPARC4, and SPARC5 instructions.
`sparcvis`	Compile for the SPARC–V9 ISA with UltraSPARC extensions. Compile for SPARC-V9 plus the Visual Instruction Set (VIS) version 1.0, and with UltraSPARC extensions. This option enables the compiler to generate code for good performance on the UltraSPARC architecture.
`sparcvis2`	Compile for the SPARC-V9 ISA with UltraSPARC-III extensions. Enables the compiler to generate object code for the UltraSPARC architecture, plus the Visual Instruction Set (VIS) version 2.0, and with UltraSPARC III extensions.
`sparcvis3`	Compile for the SPARC VIS version 3 of the SPARC-V9 ISA. Enables the compiler to use instructions from the SPARC-V9 instruction set, plus the UltraSPARC extensions, including the Visual Instruction Set (VIS) version 1.0, the UltraSPARC-III extensions, including the Visual Instruction Set (VIS) version 2.0, the fused multiply-add instructions, and the Visual Instruction Set (VIS) version 3.0
`sparcfmaf`	Compile for the `sparcfmaf` version of the SPARC-V9 ISA. Enables the compiler to use instructions from the SPARC-V9 instruction set, plus the UltraSPARC extensions, including the Visual Instruction Set (VIS) version 1.0, the UltraSPARC-III extensions, including the Visual Instruction Set (VIS) version 2.0, and the SPARC64 VI extensions for floating-point multiply-add. Note that you must use `-xarch=sparcfmaf`in conjunction with `-fma=fused` and some optimization level to get the compiler to attempt to find opportunities to use the multiply-add instructions automatically.
`sparcace`	Compile for the `sparcace` version of the SPARC-V9 ISA. Enables the compiler to use instructions from the SPARC-V9 instruction set, plus the UltraSPARC extensions, including the Visual Instruction Set (VIS) version 1.0, the UltraSPARC-III extensions, including the Visual Instruction Set (VIS) version 2.0, the SPARC64 VI extensions for floating-point multiply-add, the SPARC64 VII extensions for integer multiply-add, and the SPARC64 X extensions for ACE floating-point.
`sparcaceplus`	Compile for the `sparcaceplus` version of the SPARC-V9 ISA. Enables the compiler to use instructions from the SPARC-V9 instruction set, plus the UltraSPARC extensions, including the Visual Instruction Set (VIS) version 1.0, the UltraSPARC-III extensions, including the Visual Instruction Set (VIS) version 2.0, the SPARC64 VI extensions for floating-point multiply-add, the SPARC64 VII extensions for integer multiply-add, the SPARC64 X extensions for SPARCACE floating-point, and the SPARC64 X+ extensions for SPARCACE floating-point.
`sparcima`	Compile for the `sparcima` version of the SPARC-V9 ISA. Enables the compiler to use instructions from the SPARC-V9 instruction set, plus the UltraSPARC extensions, including the Visual Instruction Set (VIS) version 1.0, the UltraSPARC-III extensions, including the Visual Instruction Set (VIS) version 2.0, the SPARC64 VI extensions for floating-point multiply-add, and the SPARC64 VII extensions for integer multiply-add.
`v9`	Equivalent to `-m64 -xarch=sparc` Legacy makefiles and scripts that use `-xarch=v9` to obtain the 64-bit memory model need only use `-m64`.
`v9a`	Equivalent to `-m64 -xarch=sparcvis` and is provided for compatibility with earlier releases.
`v9b`	Equivalent to `-m64 -xarch=sparcvis2` and is provided for compatibility with earlier releases.

Table 3–15 details each of the -xarch keywords on x86 platforms. The default on x86 is generic (or generic64 if —m64 is specified) if -xarch is not specified.

Table 3-15 -xarch Values for x86 Platforms

`-xarch=`	Meaning (x86)
`386`	Limits instruction set to the Intel 386/486 architecture.
`pentium_pro`	Limits instruction set to the Pentium Pro architecture.
`pentium_proa`	Adds the AMD extensions (3DNow!, 3DNow! extensions, and MMX extensions) to the 32-bit Pentium Pro architecture.
`sse`	Adds the SSE instruction set to `pentium_pro`. (See Note below.)
`ssea`	Adds the AMD extensions (3DNow!, 3DNow! extensions, and MMX extensions) to the 32-bit SSE architecture.
`sse2`	Adds the SSE2 instruction set to the `pentium_pro`. (See Note below.)
`sse2a`	Adds the AMD extensions (3DNow!, 3DNow! extensions, and MMX extensions) to the 32-bit SSE2 architecture.
`sse3`	Adds the SSE3 instruction set to the SSE2 instruction set.
`sse3a`	Adds the AMD extended instructions including 3dnow to the SSE3 instruction set.
`amd64`	On Solaris platforms, this is equivalent to `-m64 -xarch=sse2` Legacy makefiles and scripts that use -`xarch=amd64` to obtain the 64-bit memory model should use `-m64`.
`amd64a`	On Solaris platforms, this is equivalent to `—m64 —xarch=sse2a`.
`sse3a`	Adds AMD extended instructions, including 3DNow! to the SSE3 instruction set.
`ssse3`	Adds the SSSE3 instructions to the SSE3 instruction set.
`sse4_1`	Adds the SSE4.1 instructions to the SSSE3 instruction set.
`sse4_2`	Adds the SSE4.2 instructions to the SSE4.1 instruction set.
`amdsse4a`	Adds the SSE4a instructions to the AMD instruction set.
`aes`	Adds the Intel Advanced Encryption Standard instruction set. Note that the compiler does not generate AES instructions automatically when `-xarch=aes` is specified unless the source code includes `.il` inline code, `_asm` statements, or assembler code that use AES instructions, or references to AES intrinsic functions.
`avx`	Uses Intel Advanced Vector Extensions instruction set.
`avx_i`	Uses Intel Advanced Vector Extensions instruction set with the RDRND, FSGSBASE and F16C instruction sets.
`avx2`	Uses Intel Advanced Vector Extensions 2 instruction set.

3.4.109.1 Special Cautions for x86/x64 Platforms:

There are some important considerations when compiling for x86 Solaris platforms.

If any part of a program is compiled or linked on an x86 platform with —m64, then all parts of the program must be compiled with one of these options as well. For details on the various Intel instruction set architectures (SSE, SSE2, SSE3, SSSE3, and so on) refer to the Intel-64 and IA-32 Intel Architecture Software Developer's Manual
Programs compiled with -xarch set to sse, sse2, sse2a, or sse3 and beyond must be run on platforms supporting these features and extensions..
With this release, the default instruction set and the meaning of -xarch=generic has changed to sse2. Now, compiling without specifying a target platform option results in an sse2 binary incompatible with older Pentium III or earlier systems.
If you compile and link in separate steps, always link using the compiler and with same -xarch setting to ensure that the correct startup routine is linked.
Arithmetic results on x86 may differ from results on SPARC due to the x86 80-byte floating-point registers. To minimize these differences, use the -fstore option or compile with -xarch=sse2 if the hardware supports SSE2.
Running programs compiled with these -xarch options on platforms that are not enabled with the appropriate features or instruction set extensions could result in segmentation faults or incorrect results occurring without any explicit warning messages.
This warning extends also to programs that employ .il inline assembly language functions or __asm() assembler code that utilize SSE, SSE2, SSE2a, and SSE3 (and beyond) instructions and extensions.

3.4.109 –xarch=isa

3.4.109.1 Special Cautions for x86/x64 Platforms:

3.4.109 `–xarch=isa`