|
04
|
|
Get CPU type from CPU registers and other methods. Save CPU type in NVRAM. NOTE: Hook routine should not alter DX, which
holds the powerup CPU ID..
|
|
06
|
|
Initialize system hardware. Reset the DMA controllers, disable the videos, clear any pending interrupts from the real-time clock and set up port B register.
|
|
07
|
|
Disable system ROM shadow and start to execute ROMEXEC code from the flash part. This task is pulled into the build only when the ROMEXEC relocation is installed.
|
|
08
|
|
Initialize chip set registers to the Initial POST Values.
|
|
09
|
|
Set in-POST flag in CMOS that indicates we are in POST. If this bit is not cleared by postClearBootFlagJ (AEh), the BIOS on next boot determines that the current configuration caused POST to fail and uses default values for configuration.
Clear the CMOS diagnostic byte (register E). Check the real-time clock and verify the battery has not lost power. Checksum the CMOS and verify it has not been corrupted (Rel. 6.0).
|
|
0A
|
|
Initialize CPU registers.
|
|
0B
|
|
Enable CPU cache. Set bits in cmos related to cache.
|
|
0C
|
|
Set the initial POST values of the cache registers if not integrated into the chipset.
|
|
0E
|
|
Set the initial POST values for registers in the integrated I/O chip.
|
|
0F
|
|
Enable the local bus IDE as primary or secondary depending on other drives detected.
|
|
10
|
|
Initialize Power Management.
|
|
11
|
|
General dispatcher for alternate register initialization. Set initial POST values for other hardware devices defined in the register tables.
|
|
12
|
|
Restore the contents of the CPU control word whenever the CPU is reset.
|
|
13
|
|
Early reset of PCI devices required to disable bus master. Assumes the presence of a stack and running from decompressed shadow memory.
|
|
14
|
|
Verify that the 8742 keyboard controller is responding. Send a self-test command to the 8742 and wait for results. Also read the switch inputs from the 8742 and write the keyboard controller command byte.
|
|
16
|
1-2-2-3
|
Verify that the ROM BIOS checksums to zero.
|
|
17
|
|
Initialize external cache before autosizing memory.
|
|
18
|
|
Initialize all three of the 8254 timers. Set the clock timer (0) to binary count, mode 3 (square wave mode), and read/write LSB then MSB. Initialize the clock timer to zero. Set the RAM refresh timer (1) to binary count, mode 2 (Rate Generator), and read/write LSB only. Set the counter to 12H to generate the refresh at the proper rate. Set sound timer (2) to binary count, mode 3, and read/write LSB, then MSB.
|
|
1A
|
|
Initialize DMA command register with these settings:
1. Memory to memory disabled
2. Channel 0 hold address disabled
3. Controller enabled
4. Normal timing
5. Fixed priority
6. Late write selection
7. DREQ sense active
8. DACK sense active low.
Initialize all 8 DMA channels with these settings:
1. Single mode
2. Address increment
3. Auto initialization disabled (channel 4 - Cascade)
4. Verify transfer
|
|
1C
|
|
Initialize interrupt controllers for some shutdowns.
|
|
20
|
1-3-1-1
|
Verify that DRAM refresh is operating by polling the refresh bit in PORTB.
|
|
22
|
1-3-1-3
|
Reset the keyboard.
|
|
24
|
|
Set segment-register addressibility to 4 GB.
|
|
28
|
|
Using the table of configurations supplied by the specific chipset module, test each DRAM configuration to see if that particular configuration is valid. Then program the chipset to its autosized configuration.
Before autosizing, disable all caches and all shadow RAM.
|
|
29
|
|
Initialize the POST Memory Manager.
|
|
2A
|
|
Zero the first 512K of RAM.
|
|
2C
|
1-3-4-1
|
Test 512K base address lines.
NOTE: If the BIOS detects error 2C, 2E, or 30 (base 512K RAM error), it displays an additional word-bitmap (xxxx) indicating the address line or bits that failed. For example, "2C 0002" means address line 1 (bit one set) has failed. "2E 1020" means data bits 12 and 5 (bits 12 and 5 set) have failed in the lower 16 bits. The BIOS also sends the bitmap to the port-80 LED display. It first displays the check point code, followed by a delay, the high-order byte, another delay, and then the low-order byte of the error. It repeats this sequence continuously.
|
|
2E
|
1-3-4-3
|
Test first 512K of RAM. See note for code 2C.
|
|
2F
|
|
Initialize external cache before shadowing.
|
|
30
|
1-4-1-1
|
RAM failure on data bits xxxx of high byte of memory bus. See note for code 2C.
|
|
32
|
|
Compute CPU speed.
|
|
33
|
|
Initialize the Phoenix Dispatch Manager.
|
|
36
|
|
Vector to proper shutdown routine.
|
|
38
|
|
Shadow the system BIOS.
|
|
3A
|
|
Autosize external cache and program cache size for enabling later in POST.
|
|
3C
|
|
If CMOS is valid, load chipset registers with values from CMOS, otherwise load defaults and display Setup prompt. If Auto Configuration is enabled, always load the chipset registers with the Setup defaults (Rel 6.0).
|
|
3D
|
|
Load alternate registers with CMOS values. Registertable pointers are in the altregtable segment.
|
|
41
|
|
Initialize extended memory for RomPilot.
|
|
42
|
|
Initialize interrupt vectors 0 thru 77h to the BIOS general interrupt handler.
|
|
45
|
|
Initialize all motherboard devices.
|
|
46
|
2-1-2-3
|
Verify the ROM copyright notice.
|
|
47
|
|
Initialize support for I2O by initializing global variables used by the I2O code. Pause POST table processing if a CMOS bit is set (for debugging).
|
|
48
|
|
Verify that the equipment specified in the CMOS matches the hardware currently installed. If the monitor type is set to 00 then a video ROM must exist. If the monitor type is 1 or 2 set the video switch to CGA. If monitor type 3, set the video switch to mono. Also specify in the equipment byte that disk drives are installed. Set appropriate status bits in CMOS or the BDA if configuration errors are found.
|
|
49
|
|
Perform these tasks:
1. Size the PCI bus topology and set bridge bus numbers.
2. Set the system max bus number.
3. Write a 0 to the command register of every PCI device.
4. Write a 0 to all 6 base registers in every PCI device.
5. Write a -1 to the status register of every PCI device.
6. Find all IOPs and initialize them.
|
|
4A
|
|
Initialize all video adapters in system.
|
|
4B
|
|
Initialize QuietBoot if it is installed. Enable both keyboard and timer interrupts (IRQ0 and IRQ1). If your POST tasks require interrupts off, preserve them with a PUSHF and CLI at the beginning and a POPF at the end. If you change the PIC, preserve the existing bits.
|
|
4C
|
|
Shadow video BIOS ROM if specified by Setup, and CMOS is valid and the previous boot was OK.
|
|
4E
|
|
Display copyright notice.
|
|
4F
|
|
Initialize MultiBoot. Allocate memory for old and new MultiBoot history tables.
|
|
50
|
|
Display CPU type and speed.
|
|
51
|
|
Checksum CMOS and initialize each EISA slot with data from the initialization data block.
|
|
52
|
|
Verify keyboard reset.
|
|
54
|
|
Initialize keystroke clicker if enabled in Setup.
|
|
55
|
|
Enable USB devices.
|
|
58
|
2-2-3-1
|
Test for unexpected interrupts. First do an STI for hot interrupts. Secondly, test the NMI for an unexpected interrupt. Thirdly, enable the parity checkers and read from memory, checking for an unexpected interrupt.
|
|
59
|
|
Register POST Display Services, fonts, and languages with the POST Dispatch Manager.
|
|
5A
|
|
Display prompt "Press F2 to enter SETUP.
|
|
5B
|
|
Disable CPU cache.
|
|
5C
|
|
Test RAM between 512K and 640K.
|
|
60
|
|
Determine and test the amount of extended memory available. Determine if memory exists by writing to a few strategic locations and see if the data can be read back. If so, perform an address-line test and a RAM test on the memory. Save the total extended memory size in the CMOS at cmosExtended.
|
|
62
|
|
Perform an address line test on A0 to the amount of memory available. This test is dependent on the processor, since the test will vary depending on the width of memory (16 or 32 bits). This test will also use A20 as the skew address to prevent corruption of the system memory.
|
|
64
|
|
Jump to UserPatch1.
|
|
66
|
|
Set cache registers to their CMOS values if CMOS is valid, unless auto configuration is enabled, in which case load cache registers from the Setup default table.
|
|
67
|
|
Quick initialization of all Application Processors in a multi-processor system.
|
|
68
|
|
Enable external cache and CPU cache if present. Configure non-cacheable regions if necessary. NOTE: Hook routine must preserve DX, which carries the cache size to the DisplayCacheSizeJ routine.
|
|
69
|
|
Initialize the handler for SMM.
|
|
6A
|
|
Display external cache size on the screen if it is non-zero. NOTE: Hook routine must preserve DX, which carries the cache size from the cacheConfigureJ routine.
|
|
6B
|
|
If CMOS is bad, load Custom Defaults from flash into CMOS. If successful, reboot.
|
|
6C
|
|
Display shadow message.
|
|
6E
|
|
Display the starting offset of the non-disposable segment of the BIOS.
|
|
70
|
|
Check flags in CMOS and in the BIOS data area for errors detected during POST. Display error messages on the screen.
|
|
72
|
|
Check status bits to see if configuration problems were detected. If so, display error messages on the screen.
|
|
76
|
|
Check status bits for keyboard-related failures. Display error messages on the screen.
|
|
7C
|
|
Initialize the hardware interrupt vectors from 08 to 0F and from 70h to 77H. Also set the interrupt vectors from 60h to 66H to zero.
|
|
7D
|
|
Initialize Intelligent System Monitoring.
|
|
7E
|
|
The Coprocessor initialization test. Use the floating point instructions to determine if a coprocessor exists instead of the ET bit in CR0.
|
|
80
|
|
Disable onboard COM and LPT ports before testing for presence of external I/O devices.
|
|
81
|
|
Run late device initialization routines.
|
|
82
|
|
Test and identify RS232 ports.
|
|
83
|
|
Configure Fixed Disk Controller.
|
|
84
|
|
Test and identify parallel ports.
|
|
85
|
|
Display any ESCD read errors and configure all PnP ISA devices.
|
|
86
|
|
Initialize onboard I/O and BDA according to CMOS and presence of external devices.
|
|
87
|
|
Initialize motherboard configurable devices.
|
|
88
|
|
Initialize interrupt controller.
|
|
89
|
|
Enable non-maskable interrupts.
|
|
8A
|
|
Initialize Extended BIOS Data Area and initialize the mouse.
|
|
8B
|
|
Setup interrupt vector and present bit in Equipment byte.
|
|
8C
|
|
Initialize both of the floppy disks and display an error message if failure was detected. Check both drives to establish the appropriate diskette types in the BIOS data area.
|
|
8F
|
|
Count the number of ATA drives in the system and update the number in bdaFdiskcount.
|
|
90
|
|
Initialize hard-disk controller. If the CMOS ram is valid and intact, and fixed disks are defined, call the fixed disk init routine to intialize the fixed disk system and take over the appropriate interrupt vectors.
|
|
91
|
|
Configure the local bus IDE timing register based on the drives attached to it.
|
|
92
|
|
Jump to UserPatch2.
|
|
93
|
|
Build the MPTABLE for multi-processor boards.
|
|
95
|
|
1. Check CMOS for CD-ROM drive present
2. Activate the drive by checking for media present
3. Check sector 11h (17) for Boot Record Volume Descriptor
4. Check the boot catalog for validity
5. Pick a boot entry
6. Create a Specification Packet
|
|
96
|
|
Reset segment-register addressibility from 4GB to normal 64K by generating a Shutdown 8.
|
|
97
|
|
Create pointer to Multi Processor table in Extended BDA.
|
|
98
|
1-2
|
Search for option ROMs. Rom scan the area from C800h for a length of BCP_ROM_Scan_Size (or to E000h by default) on every 2K boundry, looking for add on cards that need initialization.
|
|
99
|
|
Check support status for Self-Monitoring Analysis Reporting Technology (disk-failure warning).
|
|
9A
|
|
Shadow miscellaneous ROMs if specified by Setup and CMOS is valid and the previous boot was OK.
|
|
9C
|
|
Set up Power Management. Initiate power - management state machine.
|
|
9D
|
|
Initialize Security Engine.
|
|
9E
|
|
Enable hardware interrupts.
|
|
9F
|
|
Check the total number of Fast Disks (ATA and SCSI) and update the bdaFdiskCount.
|
|
A0
|
|
Verify that the system clock is interrupting.
|
|
A2
|
|
Setup Numlock indicator. Display a message if key switch is locked.
|
|
A4
|
|
Initialize typematic rate.
|
|
A8
|
|
Overwrite the "Press F2 for Setup" prompt with spaces, erasing it from the screen.
|
|
AA
|
|
Scan the key buffer to see if the F2 key was struck after keyboard interrupts were enabled. If an F2 keystroke is found, set a flag.
|
|
AC
|
|
Enter SETUP.
If (F2 was pressed)
go to SETUP
Else if (errors were found)
display "Press F1 or F2" prompt
if (F2 is pressed)
go to setup
else if (F1 is pressed)
boot
Else boot
|
|
AE
|
|
Clear ConfigFailedBit and InPostBit in CMOS.
|
|
B0
|
|
Check for errors.
If (errors were found)
beep twice
display "F1 or F2" message
if (F2 keystroke) go to SETUP
if (F1 keystroke) go to BOOT2
|
|
B1
|
|
Inform RomPilot about the end of POST.
|
|
B2
|
|
Change status bits in CMOS and/or the BIOS data area to reflect the fact that POST is complete.
|
|
B4
|
1
|
One quick beep.
|
|
B5
|
|
Turn off <Esc> and <F2> key checking.
IF (VGA adapter is present)
IF (OEM screen is still up)
Note OEM screen is gone.
Fade out OEM screen.
Reset video: clear screen, reset cursor, reload
DAC.
ENDIF
ENDIF
|
|
B6
|
|
If password on boot is enabled, a call is made to Setup to check password. If the user does not enter a valid password, Setup does not return.
|
|
B7
|
|
Initialize ACPI BIOS.
|
|
B9
|
|
Clear all screen graphics before booting.
|
|
BA
|
|
Initialize the SMBIOS header and sub-structures.
|
|
BC
|
|
Clear parity-error latch.
|
|
BD
|
|
Display Boot First menu if MultiBoot is installed.
|
|
BE
|
|
If BCP option is enabled, clear the screen before booting.
|
|
BF
|
|
Check virus and backup reminders. Display System Summary.
|
|
C0
|
|
Try to boot with INT 19.
|
|
C1
|
|
Initialize the Post Error Manager.
|
|
C2
|
|
Write PEM errors.
|
|
C3
|
|
Display PEM errors.
|
|
C4
|
|
Initialize system error handler.
|
|
C5
|
|
PnPnd dual CMOS (optional).
|
|
C6
|
|
Initialize note dock.
|
|
C7
|
|
Initialize note dock late.
|
|
C8
|
|
Force check (optional).
|
|
C9
|
|
Extended checksum (optional).
|
|
CA
|
|
Redirect Int 15h to enable target board to use remote keyboard (PICO BIOS).
|
|
CB
|
|
Redirect Int 13h to Memory Technologies Devices such as ROM, RAM, PCMCIA, and serial disk (PICO BIOS).
|
|
CC
|
|
Redirect Int 10h to enable target board to use a remote serial video (PICO BIOS).
|
|
CD
|
|
Remap I/O and memory address space for PCMCIA (PICO BIOS).
|
|
CE
|
|
Initialize digitizer device and display installed message if successful.
|
|
D2
|
|
Unknown interrupt.
|
|
The following are for Boot Block in Flash ROM
|
|
E0
|
|
Initialize the chipset.
|
|
E1
|
|
Initialize the bridge.
|
|
E2
|
|
Initialize the CPU.
|
|
E3
|
|
Initialize system timer.
|
|
E4
|
|
Initialize system I/O.
|
|
E5
|
|
Check force recovery boot.
|
|
E6
|
|
Checksum BIOS ROM.
|
|
E7
|
|
Go to BIOS.
|
|
E8
|
|
Initialize Multi Processor.
|
|
E9
|
|
Set Huge Segment.
|
|
EA
|
|
Initialilze OEM special code.
|
|
EB
|
|
Initialize PIC and DMA.
|
|
EC
|
|
Initialize Memory type.
|
|
ED
|
|
Initialize Memory size.
|
|
EE
|
|
Shadow Boot Block.
|
|
EF
|
|
System memory test.
|
|
F0
|
|
Initialize interrupt vectors.
|
|
F1
|
|
Initialize Run Time Clock.
|
|
F2
|
|
Initialize video.
|
|
F3
|
|
Initialize System Management Modem.
|
|
F4
|
1
|
Output one beep.
|
|
F5
|
|
Boot to Mini DOS.
|
|
F6
|
|
Clear Huge segment.
|
|
F7
|
|
Boot to Full DOS.
|
