5.5 Synthetic Instructions

Table 5-6 describes the mapping of synthetic instructions to hardware instructions.

Table 5-6 Synthetic Instructions and Hardware Instructions Mapping

Synthetic Instruction		Hardware Equivalents		Comment
`btst`	reg_or_imm, reg_rs1	`andcc`	reg_rs1, reg_or_imm, `%g0`	Bit test
`bset`	reg_or_imm, reg_rd	`or`	reg_rd, reg_or_imm, reg_rd	Bit set
`bclr`	reg_or_imm, reg_rd	`andn`	reg_rd, reg_or_imm, reg_rd	Bit clear
`btog`	reg_or_imm, reg_rd	`xor`	reg_rd, reg_or_imm, reg_rd	Bit toggle
`call`	reg_or_imm	`jmpl`	reg_or_imm, `%o7`
`clr`	reg_rd	`or`	`%g0`, `%g0`, reg_rd	Clear (zero) register
`clrb`	[address]	`stb`	`%g0`, [address]	Clear byte
`clrh`	[address]	`st`	`%g0`, [address]	Clear halfword
`clr`	[address]	`st`	`%g0`, [address]	Clear word
`cmp`	reg, reg_or_imm	`subcc`	reg_rs1, reg_or_imm, `%g0`	Compare
`dec`	reg_rd	`sub`	reg_rd, 1, reg_rd	Decrement by 1
`dec`	const13, reg_rd	`sub`	reg_rd, const13, reg_rd	Decrement by const13
`deccc`	reg_rd	`subcc`	reg_rd, 1, reg_rd	Decrement by 1 and set `icc`
`deccc`	const13, reg_rd	`subcc`	reg_rd, const13, reg_rd	Decrement by const13 and set `icc`
`inc`	reg_rd	`add`	reg_rd, 1, reg_rd	Increment by 1
`inc`	const13, reg_rd	`add`	reg_rd, const13, reg_rd	Increment by const13
`inccc`	reg_rd	`addcc`	reg_rd, 1, reg_rd	Increment by 1 and set `icc`
`inccc`	const13, reg_rd	`addcc`	reg_rd, const13, reg_rd	Increment by const13 and set `icc`
`jmp`	address	`jmpl`	address, `%g0`
`mov` `mov` `mov` `mov` `mov` `mov` `mov` `mov` `mov`	reg_or_imm,reg_rd `%y`, reg_rs1 `%psr`, reg_rs1 `%wim`, reg_rs1 `%tbr`, reg_rs1 reg_or_imm, `%y` reg_or_imm, `%psr` reg_or_imm, `%wim` reg_or_imm, `%tbr`	`or` `rd` `rd` `rd` `rd` `wr` `wr` `wr` `wr`	`%g0`, reg_or_imm, reg_rd `%y`, reg_rs1 `%psr`, reg_rs1 `%wim`, reg_rs1 `%tbr`, reg_rs1 `%g0`,reg_or_imm,`%y` `%g0`,reg_or_imm,`%psr` `%g0`,reg_or_imm,`%wim` `%g0`,reg_or_imm,`%tbr`
`not`	reg_rs1, reg_rd	`xnor`	reg_rs1, `%g0`, reg_rd	One's complement
`not`	reg_rd	`xnor`	reg_rd, `%g0`, reg_rd	One's complement
`neg`	reg_rs1, reg_rd	`sub`	`%g0`, reg_rs2, reg_rd	Two's complement
`neg`	reg_rd	`sub`	`%g0`, reg_rd, reg_rd	Two's complement
`restore`		`restore`	`%g0`, `%g0`, `%g0`	Trivial restore
`save`		`save`	`%g0`, `%g0`, `%g0`	Trivial save trivial save should only be used in supervisor code!
`set`	value,reg_rd	`or`	`%g0`, value, reg_rd	if -4096 ≤value ≤ 4095 Do not use the `set` synthetic instruction in an instruction delay slot.
`set`	value,reg_rd	`sethi`	`%hi`(value), reg_rd	if ((value & 0x3ff) == 0)
`set`	value, reg_rd	`sethi` `or`	`%hi`(value), reg_rd; reg_rd, `%lo`(value), reg_rd	otherwise Do not use the `set` synthetic instruction in an instruction delay slot.
`skipz`		`bnz,a .+8`		if z is set, ignores next instruction
`skipnz`		`bz,a .+8`		if z is not set, ignores next instruction
`tst`	reg	`orcc`	reg_rs1, `%g0`, `%g0`	test

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	SPARC Assembly Language Reference Manual Oracle Solaris 11 Express 11/10