E.3 SPARC-V9 Instruction Set Mapping

Table E-10 SPARC-V9 Instruction Set Mapping

Opcode	Mnemonic	Argument List	Operation	Comments
`BPA`	`ba{,a}` `{,pt\|,pn}`	%icc or %xcc, label	(Branch on cc with prediction) Branch always	1
`BPN`	`bn{,a}` `{,pt\|,pn}`	%icc or %xcc, label	Branch never	0
`BPNE`	`bne{,a}` `{,pt\|,pn}`	%icc or %xcc, label	Branch on not equal	not Z
`BPE`	`be{,a}` `{,pt\|,pn}`	%icc or %xcc, label	Branch on equal	Z
`BPG`	`bg{,a}` `{,pt\|,pn}`	%icc or %xcc, label	Branch on greater	not (Z or (N xor V))
`BPLE`	`ble{,a}` `{,pt\|,pn}`	%icc or %xcc, label	Branch on less or equal	Z or (N xor V)
`BPGE`	`bge{,a}` `{,pt\|,pn}`	%icc or %xcc, label	Branch on greater or equal	not (N xor V)
`BPL`	`bl{,a}` `{,pt\|,pn}`	%icc or %xcc, label	Branch on less	N xor V
`BPGU`	`bgu{,a}` `{,pt\|,pn}`	%icc or %xcc, label	Branch on greater unsigned	not (C or Z)
`BPLEU`	`bleu{,a}` `{,pt\|,pn}`	%icc or %xcc, label	Branch on less or equal unsigned	C or Z
`BPCC`	`bcc{,a}` `{,pt\|,pn}`	%icc or %xcc, label	Branch on carry clear (greater than or equal, unsigned)	not C
`BPCS`	`bcs{,a}` `{,pt\|,pn}`	%icc or %xcc, label	Branch on carry set (less than, unsigned)	C
`BPPOS`	`bpos{,a}` `{,pt\|,pn}`	%icc or %xcc, label	Branch on positive	not N
`BPNEG`	`bneg{,a}` `{,pt\|,pn}`	%icc or %xcc, label	Branch on negative	N
`BPVC`	`bvc{,a}` `{,pt\|,pn}`	%icc or %xcc, label	Branch on overflow clear	not V
`BPVS`	`bvs{,a}` `{,pt\|,pn}`	%icc or %xcc, label	Branch on overflow set	V
`BRZ`	`brz{,a}` `{,pt\|,pn}`	reg_rs1, label	Branch on register zero	Z
`BRLEZ`	`brlez{,a}` `{,pt\|,pn}`	reg_rs1, label	Branch on register less than or equal to zero	N or Z
`BRLZ`	`brlz{,a}` `{,pt\|,pn}`	reg_rs1, label	Branch on register less than zero	N
`BRNZ`	`brnz{,a}` `{,pt\|,pn}`	reg_rs1, label	Branch on register not zero	not Z
`BRGZ`	`brgz{,a}` `{,pt\|,pn}`	reg_rs1, label	Branch on register greater than zero	not (N or Z)
`BRGEZ`	`brgez{,a}` `{,pt\|,pn}`	reg_rs1, label	Branch on register greater than or equal to zero	not N
`CASA`	casa casa	[reg_rs1]imm_asi,reg_rs2,reg_rd [reg_rs1]%asi,reg_rs2,reg_rd	Compare and swap word from alternate space
`CASXA`	casxa casxa	[reg_rs1]imm_asi,reg_rs2,reg_rd [reg_rs1]%asi,reg_rs2,reg_rd	Compare and swap extended from alternate space
`FBPA`	`fba{,a}` `{,pt\|,pn}`	`%fccn`, `label`	(Branch on cc with prediction) Branch never	1
`FBPN`	`fbn{,a}` `{,pt\|,pn}`	`%fccn`, `label`	Branch always	0
`FBPU`	`fbu{,a}` `{,pt\|,pn}`	`%fccn`, `label`	Branch on unordered	U
`FBPG`	`fbg{,a}` `{,pt\|,pn}`	`%fccn`, `label`	Branch on greater	G
`FBPUG`	`fbug{,a}` `{,pt\|,pn}`	`%fccn`, `label`	Branch on unordered or greater	G or U
`FBPL`	`fbl{,a}` `{,pt\|,pn}`	`%fccn`, `label`	Branch on less	L
`FBPUL`	`fbul{,a}` `{,pt\|,pn}`	`%fccn`, `label`	Branch on unordered or less	L or U
`FBPLG`	`fblg{,a}` `{,pt\|,pn}`	`%fccn`, `label`	Branch on less or greater	L or G
`FBPNE`	`fbne{,a}` `{,pt\|,pn}`	`%fccn`, `label`	Branch on not equal	L or G or U
`FBPE`	`fbe{,a}` `{,pt\|,pn}`	`%fccn`, `label`	Branch on equal	E
`FBPUE`	`fbue{,a}` `{,pt\|,pn}`	`%fccn`, `label`	Branch on unordered or equal	E or U
`FBPGE`	`fbge{,a}` `{,pt\|,pn}`	`%fccn`, `label`	Branch on greater or equal	E or G
`FBPUGE`	`fbuge{,a}` `{,pt\|,pn}`	`%fccn`, `label`	Branch on unordered or greater or equal	E or G or U
`FBPLE`	`fble{,a}` `{,pt\|,pn}`	`%fccn`, `label`	Branch on less or equal	E or L
`FBPULE`	`fbule{,a}` `{,pt\|,pn}`	`%fccn`, `label`	Branch on unordered or less or equal	E or L or u
`FBPO`	`fbo{,a}` `{,pt\|,pn}`	`%fccn`, `label`	Branch on ordered	E or L or G
`FLUSHW`	`flushw`		Flush register windows
`FMOVA`	`fmov` `{s,d,q}a`	%icc or %xcc, `freg`_rs2, `freg`_rd	(Move on integer cc) Move always	1
`FMOVN`	`fmov` `{s,d,q}n`	%icc or %xcc, `freg`_rs2, `freg`_rd	Move never	0
`FMOVNE`	`fmov` `{s,d,q}ne`	%icc or %xcc, `freg`_rs2, `freg`_rd	Move if not equal	not Z
`FMOVE`	`fmov` `{s,d,q}e`	%icc or %xcc, `freg`_rs2, `freg`_rd	Move if equal	Z
`FMOVG`	`fmov` `{s,d,q}g`	%icc or %xcc, `freg`_rs2, `freg`_rd	Move if greater	not (Z or (N xor V))
`FMOVLE`	`fmov` `{s,d,q}le`	%icc or %xcc, `freg`_rs2, `freg`_rd	Move if less or equal	Z or (N xor V)
`FMOVGE`	`fmov` `{s,d,q}ge`	%icc or %xcc, `freg`_rs2, `freg`_rd	Move if greater or equal	not (N xor V)
`FMOVL`	`fmov` `{s,d,q}l`	%icc or %xcc, `freg`_rs2, `freg`_rd	Move if less	N xor V
`FMOVGU`	`fmov` `{s,d,q}gu`	%icc or %xcc, `freg`_rs2, `freg`_rd	Move if greater unsigned	not (C or Z)
`FMOVLEU`	`fmov` `{s,d,q}leu`	%icc or %xcc, `freg`_rs2, `freg`_rd	Move if less or equal unsigned	C or Z
`FMOVCC`	`fmov` `{s,d,q}cc`	%icc or %xcc, `freg`_rs2, `freg`_rd	Move if carry clear (greater or equal, unsigned)	not C
`FMOVCS`	`fmov` `{s,d,q}cs`	%icc or %xcc, `freg`_rs2, `freg`_rd	Move if carry set (less than, unsigned)	C
`FMOVPOS`	`fmov` `{s,d,q}pos`	%icc or %xcc, `freg`_rs2, `freg`_rd	Move if positive	not N
`FMOVNEG`	`fmov` `{s,d,q}neg`	%icc or %xcc, `freg`_rs2, `freg`_rd	Move if negative	N
`FMOVVC`	`fmov` `{s,d,q}vc`	%icc or %xcc, `freg`_rs2, `freg`_rd	Move if overflow clear	not V
`FMOVVS`	`fmov` `{s,d,q}vs`	%icc or %xcc, `freg`_rs2, `freg`_rd	Move if overflow set	V
`FMOVRZ`	`fmovr` `{s,d,q}e`	`reg`_rs1, `freg`_rs2, `freg`_rd	(Move f-p register on cc) Move if register zero
`FMOVRLEZ`	`fmovr` `{s,d,q}lz`	`reg`_rs1, `freg`_rs2, `freg`_rd	Move if register less than or equal zero
`FMOVRLZ`	`fmovr` `{s,d,q}lz`	`reg`_rs1, `freg`_rs2, `freg`_rd	Move if register less than zero
`FMOVRNZ` `FMOVRGZ` `FMOVRGEZ`	`fmovr` `{s,d,q}ne` `fmovr` `{s,d,q}gz` `fmovr` `{s,d,q}gez`	`reg`_rs1, `freg`_rs2, `freg`_rd `reg`_rs1, `freg`_rs2, `freg`_rd `reg`_rs1, `freg`_rs2, `freg`_rd	Move if register not zero Move if register greater than zero Move if register greater than or equal to zero
`FMOVFA` `FMOVFN` `FMOVFU` `FMOVFG` `FMOVFUG` `FMOVFL` `FMOVFUL` `FMOVFLG` `FMOVFNE` `FMOVFE` `FMOVFUE` `FMOVFGE` `FMOVFUGE` `FMOVFLE` `FMOVFULE` `FMOVFO`	`fmov{s,d,q}a` `fmov{s,d,q}n` `fmov{s,d,q}u` `fmov{s,d,q}g` `fmov{s,d,q}ug` `fmov{s,d,q}l` `fmov{s,d,q}ul` `fmov{s,d,q}lg` `fmov{s,d,q}ne` `fmov{s,d,q}e` `fmov{s,d,q}ue` `fmov{s,d,q}ge` `fmov{s,d,q}uge` `fmov{s,d,q}le` `fmov{s,d,q}ule` `fmov{s,d,q}o`	`%fcc`n`,`freg_rs2,freg_rd `%fcc`n,freg_rs2,freg_rd `%fcc`n`,`freg_rs2,freg_rd `%fcc`n`,`freg_rs2,freg_rd `%fcc`n`,`freg_rs2,freg_rd `%fcc`n`,`freg_rs2,freg_rd `%fcc`n`,`freg_rs2,freg_rd `%fcc`n`,`freg_rs2,freg_rd `%fcc`n`,`freg_rs2,freg_rd `%fcc`n`,`freg_rs2,freg_rd `%fcc`n`,`freg_rs2,freg_rd `%fcc`n`,`freg_rs2,freg_rd `%fcc`n`,`freg_rs2,freg_rd `%fcc`n`,`freg_rs2,freg_rd `%fcc`n`,`freg_rs2,freg_rd `%fcc`n`,`freg_rs2,freg_rd	(Move on floating-point cc) Move always Move never Move if unordered Move if greater Move if unordered or greater Move if less Move if unordered or less Move if less or greater Move if not equal Move if equal Move if unordered or equal Move if greater or equal Move if unordered or greater or equal Move if less or equal Move if unordered or less or equal Move if ordered	1 0 U G G or U L L or U L or G L or G or U E E or U E or G E or G or U E or L E or L or u E or L or G
`LDSW` `LDSWA`	`ldsw` `ldsw`	[address], reg_rd [regaddr] imm_asi, reg_rd	Load a signed word Load signed word from alternate space
`LDX` `LDXA` `LDXFSR`	`ldx` `ldxa` `ldxa` `ldx`	[address], reg_rd [regaddr] imm_asi, reg_rd [reg_plus_imm] %asi, reg_rd [address], %fsr	Load extended word Load extended word from alternate space Load floating-point state register
`MEMBAR`	`membar`	membar_mask	Memory barrier
`MOVA` `MOVN` `MOVNE` `MOVE` `MOVG` `MOVLE` `MOVGE` `MOVL` `MOVGU` `MOVLEU` `MOVCC` `MOVCS` `MOVPOS` `MOVNEG` `MOVVC` `MOVVS`	`mova` `movn` `movne` `move` `movg` `movle` `movge` `movl` `movgu` `movleu` `movcc` `movcs` `movpos` `movneg` `movvc` `movvs`	%icc or %xcc, `reg_or_imm11, reg`_rd %icc or %xcc, `reg_or_imm11, reg`_rd %icc or %xcc, `reg_or_imm11, reg`_rd %icc or %xcc, `reg_or_imm11, reg`_rd %icc or %xcc, `reg_or_imm11, reg`_rd %icc or %xcc, `reg_or_imm11, reg`_rd %icc or %xcc, `reg_or_imm11, reg`_rd %icc or %xcc, `reg_or_imm11, reg`_rd %icc or %xcc, `reg_or_imm11, reg`_rd %icc or %xcc, `reg_or_imm11, reg`_rd %icc or %xcc, `reg_or_imm11, reg`_rd %icc or %xcc, `reg_or_imm11, reg`_rd %icc or %xcc, `reg_or_imm11, reg`_rd %icc or %xcc, `reg_or_imm11, reg`_rd %icc or %xcc, `reg_or_imm11, reg`_rd %icc or %xcc, `reg_or_imm11, reg`_rd	(Move integer register on cc) Move always Move never Move if not equal Move if equal Move if greater Move if less or equal Move if greater or equal Move if less Move if greater unsigned Move if less or equal unsigned Move if carry clear (greater or equal, unsigned) Move if carry set (less than, unsigned) Move if positive Move if negative Move if overflow clear Move if overflow set	1 0 not Z Z not (Z or (N xor V)) Z or (N xor V) not (N xor V) N xor V not (C or Z) C or Z not C C not N N not V V
`MOVFA` `MOVFN` `MOVFU` `MOVFG` `MOVFUG` `MOVFL` `MOVFUL` `MOVFLG` `MOVFNE` `MOVFE` `MOVFUE` `MOVFGE` `MOVFUGE` `MOVFLE` `MOVFULE` `MOVFO`	`mova` `movn` `movu` `movg` `movug` `movl` `movul` `movlg` `movne` `move` `movue` `movge` `movuge` `movle` `movule` `movo`	`%fcc`n`,`reg_or_imm11`,`reg_rd `%fcc`n,reg_or_imm11`,`reg_rd `%fcc`n`,`reg_or_imm11`,`reg_rd `%fcc`n`,`reg_or_imm11`,`reg_rd `%fcc`n`,`reg_or_imm11`,`reg_rd `%fcc`n`,`reg_or_imm11`,`reg_rd `%fcc`n`,`reg_or_imm11`,`reg_rd `%fcc`n`,`reg_or_imm11`,`reg_rd `%fcc`n`,`reg_or_imm11`,`reg_rd `%fcc`n`,`reg_or_imm11`,`reg_rd `%fcc`n`,`reg_or_imm11`,`reg_rd `%fcc`n`,`reg_or_imm11`,`reg_rd `%fcc`n,reg_or_imm11,reg_rd `%fcc`n`,`reg_or_imm11`,`reg_rd `%fcc`n`,`reg_or_imm11`,`reg_rd `%fcc`n`,`reg_or_imm11`,`reg_rd	(Move on floating-point cc) Move always Move never Move if unordered Move if greater Move if unordered or greater Move if less Move if unordered or less Move if less or greater Move if not equal Move if equal Move if unordered or equal Move if greater or equal Move if unordered or greater or equal Move if less or equal Move if unordered or less or equal Move if ordered	1 0 U G G or U L L or U L or G L or G or U E E or U E or G E or G or U E or L E or L or u E or L or G
`MOVRZ` `MOVRLEZ` `MOVRLZ` `MOVRNZ` `MOVRGZ` `MOVRGEZ`	`movre` `movrlez` `movrlz` `movrnz` `movrgz` `movrgez`	reg_rs1, reg_or_imm10,reg_rd reg_rs1, reg_or_imm10,reg_rd reg_rs1, reg_or_imm10,reg_rd reg_rs1, reg_or_imm10,reg_rd reg_rs1, reg_or_imm10,reg_rd reg_rs1, reg_or_imm10,reg_rd	(Move register on register cc) Move if register zero Move if register less than or equal to zero Move if register less than zero Move if register not zero Move if register greater than zero Move if register greater than or equal to zero	Z N or Z N not Z N nor Z not N
`MULX`	`mulx`	reg_rs1, reg_or_imm,reg_rd	(Generic 64-bit Multiply) Multiply (signed or unsigned)	See SDIVX and UDIVX
`POPC`	`popc`	reg_or_imm, reg_rd	Population count
`PREFETCH` `PREFETCHA`	`prefetch` `prefetcha` `prefetcha`	[address], prefetch_dcn [regaddr] imm_asi, prefetch_fcn [reg_plus_imm] `%asi`, prefetch_fcn	Prefetch data Prefetch data from alternate space	See The SPARC architecture manual, version 9
`SDIVX`	`sdivx`	reg_rs1, reg_or_imm,reg_rd	(64-bit signed divide) Signed Divide	See MULX and UDIVX
`STX` `STXA` `STXFSR`	`stx` `stxa` `stxa` `stx`	reg_rd, [address] reg_rd, [address] imm_asi reg_rd, [reg_plus_imm] %asi %fsr, [address]	Store extended word Store extended word into alternate space Store floating-point register (all 64-bits)
`UDIVX`	`udivx`	reg_rs1, reg_or_imm, reg_rd	(64-bit unsigned divide) Unsigned divide	See MULX and SDIVX

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