Contents

Netra CP3010 Board User's Guide

819-1183-10

Contents

1. Introduction to the Netra CP3010 Board

1.1 Overview of the Netra CP3010 Board

1.2 Features of the Netra CP3010 Board

1.3 Netra CP3010 Board System Configurations

1.3.1 PMC and PIM Modules

1.3.2 Rear Transition Card

1.4 Hot-Swap Support

1.5 System Requirements

1.5.1 Hardware Requirements

1.5.2 Software Requirements

1.6 Technical Support and Warranty

1.6.1 Board Part Number, Serial Number, and Revision Number Identification

2. Hardware Installation

2.1 Equipment and Operator Safety

2.2 Materials and Tools Required

2.3 Preparing for the Installation

2.3.1 Checking Power, Thermal, Environmental, and Space Requirements

2.3.2 Determining Local Network IP Addresses and Host Names

2.3.3 Installation Procedure Summary

2.4 Configuring the Board Hardware

2.4.1 Installation of DDR-1 DIMM Memory Modules

2.4.1.1 Installing a DDR-1 DIMM Memory Module

2.4.1.2 Removing a DDR-1 DIMM Memory Module

2.4.2 Installation of Optional TOD Battery

2.4.3 Installation of Optional Compact Flash Card

2.4.4 Installation of Optional PMC Devices

2.4.4.1 Installing an Optional PMC Device

2.4.5 Setting Switches

2.4.6 Replacing the EEPROM

2.4.7 Configuring Rear Transition Card Hardware

2.4.7.1 Installing PIM Assemblies

2.5 Installing the Netra CP3010 Board

2.5.1 Installing the Netra CP3010 Board With a Rear Transition Card

2.5.1.1 Installing a Rear Transition Card

2.5.2 Installing the Netra CP3010 Board

2.6 Connecting External I/O Cables

3. Software Configuration

3.1 Operating Systems

3.2 Installing Diskless Clients

3.2.1 Creating a Boot Server for Diskless Clients

3.2.2 Adding a Diskless Client

3.3 Hot Swap Information

3.3.1 Hot-Swapping the Netra CP3010 Board

3.3.1.1 Hot-Swap LED

3.4 Retrieving Device Information

3.5 Downloading and Installing SunVTS Software

4.1 Power-On Self-Test Diagnostics

4.1.1 Controlling POST Diagnostics

4.1.2 Starting POST Diagnostics

4.2 OpenBoot PROM Commands

4.2.1 Running OpenBoot PROM Commands

4.2.1.1 Network Device Aliases

4.2.2 probe-scsi and probe-scsi-all Commands

4.2.3 probe-ide Command

4.2.4 show-devs Command

4.3 OpenBoot Diagnostics

4.4 Recent Diagnostic Test Results

4.4.1 Viewing Recent Test Results

4.5 OpenBoot Configuration Variables

4.5.1 Viewing and Setting OpenBoot Configuration Variables

4.5.2 Using the watch-net and watch-net-all Commands to Check the Network Connections

4.6 Firmware Memory Map

4.7 Automatic System Reconfiguration

4.7.1 Setting Autoboot Options

4.7.2 Error-Handling Summary

4.7.3 Reset Scenarios

4.7.4 Enabling ASR

4.7.5 Disabling ASR

5. Hardware and Functional Description

5.1 Hardware Architecture

5.1.1 UltraSPARC IIIi Processor

5.1.1.1 Overview

5.1.1.2 UltraSPARC IIIi Processor Speed

5.1.1.3 UltraSPARC IIIi Processor Package

5.1.1.4 UltraSPARC IIIi Processor Socket

5.1.2 DDR Memory Subsystem

5.1.2.1 Key Features

5.1.2.2 ECC Checking and Generation

5.1.2.3 Serial Presence Detect

5.1.3.1 JBus Device Arbitration

5.1.3.2 JBus Device Mapping

5.1.3.3 JBus Boot Path

5.1.3.4 JBus Termination Scheme

5.1.4 I/O Subsystem

5.1.4.1 JBus-PCI ASICs

5.1.4.2 10/100/1000BASE-T Ethernet (Base Fabric)

5.1.5 Intelligent Platform Management Controller (IPMC)

5.1.5.1 Payload Interface

5.1.5.2 Intelligent Platform Management Bus (IPMB)

5.1.5.3 Hot-Swap Latch and LEDs

5.1.5.4 Payload Power Control

5.1.5.5 Payload Base and Fabric Interface E-Keying Control

5.1.5.6 IMPI and Sun FRU Information

5.1.5.7 Netconsole Connectivity to Base Fabric Chipset

5.1.5.8 System Monitor (ADM1026) and Thresholds

5.1.5.9 I²C Architecture

5.2.1 Interrupt Transactions

5.2.3 Southbridge Chip Interrupts

5.2.4 JBus-PCI ASIC Interrupt Processing

5.2.5 Bus Error Interrupts

5.2.6 H8 Interrupts

5.3.1 Hard Reset

5.3.2 Soft Reset

5.3.3 Externally Initiated Reset (XIR)

5.3.4 PCI Resets

5.3.4.1 PCI Devices

5.3.4.2 Southbridge Chip

5.3.4.3 IPMC Reset

5.3.5 Processor Internal Resets

5.3.5.1 Software-Initiated Reset (SIR)

5.3.5.2 Watchdog Reset (WDR)

5.4.1 System Clock Sources

5.4.2 JBus Device Clocks

5.4.2.1 JBus Clock Generator

5.4.2.2 CPU and Memory Clock Frequency Selection

5.4.2.3 JBus Device Clock Programming

5.4.2.4 JBus Clock Generator Programming

5.4.3 STICK Clock

5.4.3.1 STICK Timer

5.4.4 PCI Device Clocks

5.4.5 IO Device Clocks

5.4.5.1 RTC Clock

5.4.5.2 Ethernet Clocks

5.4.5.3 SAS Clock

5.4.5.4 IPM Controller Clock

5.5 Power Requirements

5.5.2 ATCA Power Module (-48V to 12V)

5.5.3 On-Board Voltage Converters

5.5.4 CPU Core Power

5.5.4.1 DDR Memory Power

5.5.4.2 DTL I/O Power

5.5.4.3 DDR Memory Termination Power (Vtt)

5.5.4.4 JBus-PCI ASIC Power

5.5.4.5 Ethernet Controller Power

5.5.4.6 SAS Controller Power

A. Physical Characteristics

A.1 Form Factor

A.2 Thermal Management

A.4 Front Panel

A.4.1 Visual Indicators

A.5 Switches and Jumpers

A.6 Connectors and Pinout

A.6.1 Front Panel Connectors

A.6.1.1 Ethernet Ports

A.6.1.2 Serial Ports

A.6.1.3 SAS Port

A.6.2 PMC Connectors

A.6.3 Backplane Power Connector (Zone 1)

A.6.4 Data Transport Connector (Zone 2)

A.6.5 RTM Connector (Zone 3)

B. Sun OEM IPMI Commands

B.1 Get Version Command

B.2 Set Boot Page Command

B.3 Get Boot Page Command

B.4 Set Front Panel Reset Button State Command

B.5 Get Front Panel Reset Button State Command

B.6 Set Ethernet Force Front Bit Command

B.7 Get Ethernet Force Front Bit Command

B.8 Get RTM Status Command

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