The PCI Express features of the HBA include the following:
Provides 4 or 8 PCI Express PHYs
Supports a single-PHY (one lane) link transfer rate up to 6.0 Gb/s in each direction
Supports link widths of x8, x4, and x1
Automatically downshifts to a x4-link width if plugged into a x8 connector that is wired as a x4 connector
Provides a scalable interface:
Single-lane aggregate bandwidth of up to 0.5 GB/s (500 MB/s)
Quad-lane aggregate bandwidth of up to 2.0 GB/s (2000 MB/s)
Eight-lane aggregate bandwidth of up to 4.0 GB/s (4000 MB/s)
Supports serial, point-to-point interconnections between devices:
Reduces the electrical load of the connection
Enables higher transmission and reception frequencies
Supports lane reversal and polarity inversion
Supports PCI Express hot plugging
Supports power management
Supports PCI Power Management 1.2:
Supports active-state power management (ASPM), including the L0, L0s, L1 states, by placing links in a power-savings mode when there is no link activity
Contains a replay buffer that preserves a copy of the data for retransmission in case a cyclic redundancy check (CRC) error occurs
Supports the PCI Express advanced error-reporting capabilities
Uses a packetized and layered architecture
Achieves high bandwidth per pin with low overhead and low latency
Provides software compatibility with PCI and PCI-X software:
Leverages existing PCI device drivers
Supports the memory, I/O, and configuration address spaces
Supports memory read/write transactions, I/O read/write transactions, and configuration read/write transactions
Provides 4 KB of PCI configuration address space per device
Supports posted and nonposted transactions
Provides quality-of-service (QOS) link configuration and arbitration policies
Supports Traffic Class 0 and one virtual channel
Supports message-signaled interrupts (both MSI and MSI-X) as well as INTx interrupt signaling for legacy PCI support
Supports end-to-end CRC (ECRC) and advanced error reporting