generic_events - generic performance counter events
The Oracle Solaris cpc(3CPC) subsystem implements a number of predefined, generic performance counter events. Each generic event maps onto a single platform specific event and one or more optional attributes. Each hardware platform only need support a subset of the total set of generic events.
The defined generic events are:
Conditional branch instructions
Branch instructions
Conditional branch instructions mispredicted
Conditional branch instructions not taken
Conditional branch instructions correctly predicted
Conditional branch instructions taken
Unconditional branch instructions
Cycles branch units are idle
Branch target address cache misses
Requests for exclusive access to clean cache line
Requests for cache invalidation
Requests for cache line intervention
Request for exclusive access to shared cache line
Request for cache snoop
Failed conditional store instructions
Successful conditional store instructions
Total conditional store instructions
Floating point add instructions
Floating point divide instructions
Floating point multiply and add instructions
Floating point multiply instructions
Floating point inverse instructions
Floating point instructions
Floating point operations
Cycles the floating point unit stalled
Cycles the floating point units are idle
Floating point sqrt instructions
Cycles with maximum instructions completed
Cycles with maximum instruction issue
Cycles when units are idle
Hardware interrupts
Integer instructions
Total cycles
Instructions issued
Instructions completed
VectorSIMD instructions
Level 1 data cache accesses
Level 1 data cache hits
Level 1 data cache misses
Level 1 data cache reads
Level 1 data cache writes
Level 1 instruction cache accesses
Level 1 instruction cache hits
Level 1 instruction cache misses
Level 1 instruction cache reads
Level 1 instruction cache writes
Level 1 cache load misses
Level 1 cache store misses
Level 1 cache accesses
Level 1 cache hits
Level 1 cache misses
Level 1 cache reads
Level 1 cache writes
Level 2 data cache accesses
Level 2 data cache hits
Level 2 data cache misses
Level 2 data cache reads
Level 2 data cache writes
Level 2 instruction cache accesses
Level 2 instruction cache hits
Level 2 instruction cache misses
Level 2 instruction cache reads
Level 2 instruction cache writes
Level 2 cache load misses
Level 2 cache store misses
Level 2 cache accesses
Level 2 cache hits
Level 2 cache misses
Level 2 cache reads
Level 2 cache writes
Level 3 data cache accesses
Level 3 data cache hits
Level 3 data cache misses
Level 3 data cache reads
Level 3 data cache writes
Level 3 instruction cache accesses
Level 3 instruction cache hits
Level 3 instruction cache misses
Level 3 instruction cache reads
Level 3 instruction cache writes
Level 3 cache load misses
Level 3 cache store misses
Level 3 cache accesses
Level 3 cache hits
Level 3 cache misses
Level 3 cache reads
Level 3 cache writes
Load Instructions
Loadstore Instructions
Cycles load store units are idle
Cycles stalled waiting for memory reads
Cycles stalled waiting for memory accesses
Cycles stalled waiting for memory writes
Data prefetch cache misses
Cycles stalled on any resource
Store Instructions
Cycles with no instructions completed
Synchronization instructions completed
Data TLB misses
Instruction TLB misses
TLB shootdowns
Total TLB misses
The tables below define mappings of generic events to platform events and any associated attribute for all supported platforms.
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Fixed-function counters do not require Event Code and Unit Mask. The generic event to fixed-function counter event mappings available are:
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For fixed-function counter mappings refer to the Intel Core2 listing above.
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For fixed-function counter mappings refer to the Intel Core2 listing above.
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See attributes(7) for descriptions of the following attributes:
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Generic names prefixed with “PAPI_” are taken from the University of Tennessee's PAPI project, https://icl.cs.utk.edu/papi.