JavaScript is required to for searching.
Skip Navigation Links
Exit Print View
Netra SPARC T3-1BA Blade Server User’s Guide
search filter icon
search icon

Document Information

Using This Documentation

UNIX Commands

Shell Prompts

Related Documentation

Documentation, Support, and Training

Evaluating Product Compatibility

Evaluating the Blade Server

Features

Front and Side Panels

Form-Factor Physical Characteristics

Block Diagram

SPARC T3 Processor

Memory Support

Service Processor

Networking and I/O

IPMC

IPMB

FPGA

ARTM Support

Hot-Swap Support

Ports and Connectors

System Watchdog Timers

Warranty and Technical Support

Qualifying Your System

System Configurations

System Requirements and Options

Installing Optional Components

Install an ARTM

Install Compact Flash

Install Onboard Memory

Installing the Blade Server

Preparing to Install the Blade Server

Environmental Requirements

Power and Thermal Distribution

Required Cooling and Blade Impedance Curve

Tools and Materials Needed

Local Network IP Addresses and Host Names

Safety Requirements

Upgrade the Fan Trays

Installing the Blade Server

Unpack the Blade Server

Install Optional Components

Connect the External I/O Cables

Connect Cables to a System Console Running the Oracle Solaris OS

Connect Cables to a System Console Not Running Oracle Solaris OS

Insert and Latch the Blade Server

Operating System and Patches

Software and Firmware Upgrades

Administering the System

Software and Firmware Upgrades

Firmware and Blade Server Management

Creating a Boot Disk Server and Adding Clients

Create a Boot Server for Diskless Clients

Add Diskless Clients

Connect Hosts to LAN

Compact Flash Formatting for the Oracle Solaris OS

Automatic Power-Off Events

Performing a Server Recovery

Administering Configurations

ShMM CLI and Commands

Electronic Blade Server ID

View Blade ID

View Midplane FRU Information

Change the OOS LED Color

Multiplex Configuration of Zones 2 and 3

Management Port Routing

Configuring Ports and Pins

Front Connectors

On-Board Connectors

Midplane Connectors

Advanced Rear Transition Module Connectors (Zone 3)

Administering the Network

Locate Base MAC Address on Blade Server

Configuring and Using Serial Over LAN

Log In to Oracle ILOM

Servicing the Blade Server

LEDs and Status Indicators

Reset the Blade Server

Replacing a Blade Server

Shut Down OS and Deactivate the Blade Server

Power Off and Remove the Blade Server

Removing Optional Components

Power Off and Remove an ARTM

Remove a Compact Flash Card

Remove Onboard Memory

Replace a TOD Clock Battery

Return a Blade Server

Part Number, Serial Number, and MAC Address Label Locations

Programming the Blade Server

Programmable Devices

Sensors

OEM and IPMI Commands

Glossary

Index

SPARC T3 Processor

The SPARC T3 multicore processor is the basis of the blade server. The SPARC T3 processor is based on CMT technology that is optimized for highly threaded transactional processing. The SPARC T3 processor improves throughput while using less power and dissipating less heat than conventional processor designs. It is a high-performance, highly integrated processor that implements the 64-bit SPARC V9 architecture. On the blade server, the SPARC T3 processor operates at 1.4 GHz and contains 16 Kbytes of instruction cache per core and 8 Kbytes of data cache per core.

The processor supports 12 SPARC processor cores, and each core is capable of supporting 8 threads for a total of 96 threads.

Each SPARC physical processor core has full hardware support for eight strands, two integer execution pipelines, one floating-point execution pipeline, and one memory pipeline. The 12 SPARC cores are connected through a crossbar to an on-chip unified 4-Mbyte, 16-way associative L2 cache.

There are two on-chip memory controllers that interface directly to FB-DIMM memory and include eight FB-DIMM slots (one per channel, or two per memory controller). In addition, an on-chip PCI-Express I/O interface and two 10-Gb Ethernet ports are available. The SPARC T3 processor is a highly integrated processor.