Documentation, Support, and Training
Evaluating Product Compatibility
Form-Factor Physical Characteristics
Warranty and Technical Support
System Requirements and Options
Installing Optional Components
Preparing to Install the Blade Server
Power and Thermal Distribution
Required Cooling and Blade Impedance Curve
Local Network IP Addresses and Host Names
Connect the External I/O Cables
Connect Cables to a System Console Running the Oracle Solaris OS
Connect Cables to a System Console Not Running Oracle Solaris OS
Insert and Latch the Blade Server
Software and Firmware Upgrades
Software and Firmware Upgrades
Firmware and Blade Server Management
Creating a Boot Disk Server and Adding Clients
Create a Boot Server for Diskless Clients
Compact Flash Formatting for the Oracle Solaris OS
Multiplex Configuration of Zones 2 and 3
Advanced Rear Transition Module Connectors (Zone 3)
Locate Base MAC Address on Blade Server
Configuring and Using Serial Over LAN
Shut Down OS and Deactivate the Blade Server
Power Off and Remove the Blade Server
The SPARC T3 multicore processor is the basis of the blade server. The SPARC T3 processor is based on CMT technology that is optimized for highly threaded transactional processing. The SPARC T3 processor improves throughput while using less power and dissipating less heat than conventional processor designs. It is a high-performance, highly integrated processor that implements the 64-bit SPARC V9 architecture. On the blade server, the SPARC T3 processor operates at 1.4 GHz and contains 16 Kbytes of instruction cache per core and 8 Kbytes of data cache per core.
The processor supports 12 SPARC processor cores, and each core is capable of supporting 8 threads for a total of 96 threads.
Each SPARC physical processor core has full hardware support for eight strands, two integer execution pipelines, one floating-point execution pipeline, and one memory pipeline. The 12 SPARC cores are connected through a crossbar to an on-chip unified 4-Mbyte, 16-way associative L2 cache.
There are two on-chip memory controllers that interface directly to FB-DIMM memory and include eight FB-DIMM slots (one per channel, or two per memory controller). In addition, an on-chip PCI-Express I/O interface and two 10-Gb Ethernet ports are available. The SPARC T3 processor is a highly integrated processor.