DIMM and Processor Physical Layout
The physical layout of the DIMMs
and processor(s) is shown in the following figure. When viewing the
server from the front, processor 0 (P0) is on the left. Notice that each processor,
P0 and P1, has four memory channels that are labeled, from left to right, Ch C, Ch
D, Ch B, and Ch A.
Figure 5 DIMM and Processor Physical Layout
In single-processor systems, the DIMM sockets associated with the processor 1
(P1) are nonfunctional and should not be populated with DIMMs. A maximum of 12
DIMMs are supported in single-processor systems and the DIMMs must be installed
in DIMM sockets associated with the P0 processor socket.