The DIMM population rules are as follows:
Do not populate any DIMM sockets next to an empty CPU socket. Each processor contains a separate memory controller.
Each CPU can support a maximum of:
Nine dual-rank (DR) or single-rank (SR) DIMMs; or
Six quad-rank (QR) DIMMs with two per memory channel; or
Three QR DIMMs with one per channel and three DR or SR DIMMs.
Populate DIMMs by location according to the following rules (see DIMM and CPU Physical Layout for DIMM slot numbering):
Populate the DIMM slots for each memory channel that are the farthest from the CPU first.
For example, populate D8/D5/D2 first; then D7/D4/D1 second; and finally, D6/D3/D0.
Populate QR DIMMs first, followed by SR or DR DIMMs.
Populate QR DIMMs in blue sockets (D8/D5/D2) first then white sockets (D7/D4/D1).
Note that QR DIMMs are supported only in white sockets if adjacent blue socket contains a QR DIMM.
Populate QR, SR, or DR DIMMs in sets of three for each CPU, one per memory channel.
For maximum performance, apply the following rules:
Preserve DIMM symmetry to ensure the best performance. For example, add 3x of same kind DIMMs, one per memory channel. Also, if the server has two CPUs, ensure that both CPUs have the same size of DIMMs populated in the same manner.
In certain configurations, DIMMs will run slower than their individual maximum speed. See DIMM Considerations and Limitations for more information.