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Updated: Wednesday, February 9, 2022

tblgen (1)


tblgen - Target Description To C++ Code Generator


tblgen [options] [filename]


TBLGEN(1)                            LLVM                            TBLGEN(1)

       tblgen - Target Description To C++ Code Generator

       tblgen [options] [filename]

       tblgen  translates  from  target  description (.td) files into C++ code
       that can be included in the definition of an LLVM target library.  Most
       users  of  LLVM  will  not  need  to  use this program.  It is only for
       assisting with writing an LLVM target backend.

       The input and output of tblgen is beyond the scope of this short intro-
       duction; please see the introduction to TableGen.

       The  filename argument specifies the name of a Target Description (.td)
       file to read as input.

       -help  Print a summary of command line options.

       -o filename
              Specify the output file name.  If filename  is  -,  then  tblgen
              sends its output to standard output.

       -I directory
              Specify  where to find other target description files for inclu-
              sion.  The directory value should be a full or partial path to a
              directory that contains target description files.

       -asmparsernum N
              Make -gen-asm-parser emit assembly writer number N.

       -asmwriternum N
              Make -gen-asm-writer emit assembly writer number N.

       -class className
              Print the enumeration list for this class.

              Print all records to standard output (default).

              Print enumeration values for a class.

              Print expanded sets for testing DAG exprs.

              Generate machine code emitter.

              Generate registers and register classes info.

              Generate instruction descriptions.

              Generate the assembly writer.

              Generate disassembler.

              Generate pseudo instruction lowering.

              Generate a DAG (Directed Acycle Graph) instruction selector.

              Generate assembly instruction matcher.

              Generate DFA Packetizer for VLIW targets.

              Generate a "fast" instruction selector.

              Generate subtarget enumerations.

              Generate intrinsic information.

              Generate target intrinsic information.

              Generate enhanced disassembly info.

              Show the version number of this program.

       If  tblgen  succeeds,  it  will  exit  with  0.  Otherwise, if an error
       occurs, it will exit with a non-zero value.

       Maintained by The LLVM Team (http://llvm.org/).

       2003-2016, LLVM Project

       See attributes(7) for descriptions of the following attributes:

       |Availability   | developer/llvm/llvm |
       |Stability      | Uncommitted         |

       Source code for open source software components in Oracle  Solaris  can
       be found at https://www.oracle.com/downloads/opensource/solaris-source-

       This    software    was    built    from    source     available     at
       https://github.com/oracle/solaris-userland.    The  original  community
       source    was    downloaded     from      https://github.com/llvm/llvm-

       Further information about this software can be found on the open source
       community website at https://llvm.org/.

3.8                               2016-07-10                         TBLGEN(1)